Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
1998-05-06
2001-07-31
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S112000
Reexamination Certificate
active
06268748
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to computer memory or logic modules, and more particularly to memory or logic modules utilizing low leakage driver circuits and to a method of operating such modules in a low leakage mode.
BACKGROUND OF THE INVENTION
Multiple memory units such as Dynamic Random Access Memory units (DRAMs) and logic units, such as Application Specific Integrated Circuits (ASICs) and Microprocessors, utilized in computers for the storage and retrieval of data computations and etc., in conjunction with driver circuits, are generally provided in integrated circuit packages, or computer memory or logic modules. In these integrated circuit packages, leakage currents are a well known problem, and a major source of such leakage currents are the driver circuits. Conventionally, a large numbers of field effect transistors (FETs) are utilized as drivers, and while the leakage of any single driver transistor is generally rather small, the overall leakage of the circuit package is usually quite extensive due to the number of drivers employed.
In conventional driver circuits of the prior art, the system ground is applied to the gates of inactive transistors. The gate to source voltage (Vgs) of these transistors remains at or slightly above ground. The channel lengths of the FET transistors are chosen to be long enough to avoid unwanted leakage current. Generally, the accumulative leakage current requires construction of driver devices having minimum leakage, and the latter, in turn, places severe limitations on chip design, especially slower performance and greater chip area requirements.
An arrangement for reducing driver leakage in off chip driver circuits is described in U.S. Pat. No. 5,257,238, issued to Ruojia Lee et al on Oct. 26, 1993, wherein the leakage in the driver circuit is reduced by applying a negative bias, rather than simply ground voltage, to the inactive driver transistors. Now, while this arrangement results in a more complete turn off of the inactive transistors, and thus a reduction in leakage, it requires considerably more time to bring the negatively biased transistors up to an active state. Consequently, the speed of this prior art arrangement suffers accordingly.
SUMMARY OF THE INVENTION
Broadly, the invention comprises a memory or logic module and method having a driver circuit operating with reduced driver leakage. In accordance with the invention, the memory or logic module includes means responsive to a given operation of the module for simultaneously applying a first positive gate bias to a first number of driver transistors to place them in an operational state, a second positive gate bias to a second number of driver transistors to place them in a state of readiness for subsequent operation, and a negative gate bias to the remaining driver transistors to place them in a full off, or inactive condition and thereby reduce noise sensitivity and leakage current in the driver circuit. In this arrangement, the number of transistors to which the second positive bias is applied, are transistors which are anticipated to at least include the driver transistors which are anticipated as necessary for activation in the next subsequent operation of the module.
The means for applying the first and second positive biases and the negative bias to the select transistors groups, further includes means responsive to the next subsequent given operation of the module for applying the first positive bias to at least some of the second select number of transistors to activate them from their state of readiness to an operational state, and the second positive bias to another select number of said transistors, which have been determined as including those transistors likely to be next activated, and the negative bias to the new remainder of the transistors to place them in their full off condition.
Accordingly, it is an object of the present invention to provide a memory or logic module having reduced leakage.
Another object of the present invention is to provide a memory or logic module including a driver circuit operable in a low leakage mode.
Still another object of the present invention is to provide a memory or logic module of reduced leakage in conjunction with area efficient, driver transistor layouts.
A further object of the present invention is to provide a method of operating a computer memory or logic function in a reduced leakage mode.
These and other objects and features of the present invention will become further apparent from the following description taken in conjunction with the drawings.
REFERENCES:
patent: 4709162 (1987-11-01), Braceras et al.
patent: 5257238 (1993-10-01), Lee et al.
patent: 5450025 (1995-09-01), Shay
patent: 5467031 (1995-11-01), Nugyen et al.
patent: 5513146 (1996-04-01), Atsumi et al.
patent: 5654913 (1997-08-01), Fukushima et al.
patent: 5838177 (1998-11-01), Keeth
Bertin Claude L.
Fifield John A.
Houghton Russell J.
Miller Christopher P.
Tonti William R.
International Business Machines Corp.
Lam Tuan T.
Thornton David R.
Thornton & Thornton
Walsh Robert A.
LandOfFree
Module with low leakage driver circuits and method of operation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Module with low leakage driver circuits and method of operation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Module with low leakage driver circuits and method of operation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2496115