Module interconnection testing scheme

Details Module interconnection testing scheme Module interconnection testing scheme

1978-08-18

1980-12-23

Strecker, Gerard R.

Electricity: measuring and testing

Plural, automatically sequential tests

324 51, 371 25, G01R 3102, G01R 3128

Patent

active

042413079

ABSTRACT:
This specification describes the testing of interconnections between modules mounted on a card and between the modules and the input and output terminals of the card. Each of the modules has an Exclusive-OR circuit which receives an input from each of the input pins of the module and has a single output which is taken off an output pin of the module. Also, each of the modules has a test input circuit for accessing all of the output pins of the module in parallel from a single input terminal. The test input circuits are used to apply a binary 0 followed by a binary 1 to all the outputs of all the modules. The Exclusive-OR circuits are used to monitor the response to those signals. By testing in this manner, all the connections between the modules and also between the modules and the card terminals can be checked for stuck ones and zeros. In the preferred embodiment a more complex but still relatively simple bit pattern can test all the interconnection nets to determine if there are shorts between any of the nets.

REFERENCES:
patent: 3746973 (1973-07-01), McMahon
patent: 3781683 (1973-12-01), Freed
patent: 3789205 (1974-01-01), James
patent: 3803483 (1974-04-01), McMahon
patent: 3815025 (1974-06-01), Jordan
patent: 4055754 (1977-10-01), Chesley
patent: 4140967 (1979-02-01), Balasubamanian et al.
Chao et al., Online Minimum Probing LSI Testing System, IBM Tech. Discl. Bulletin, vol. 17, No. 1, Jun. 1974, pp. 152, 153.

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