Multiplex communications – Duplex – Transmit/receive interaction control
Reexamination Certificate
2004-01-16
2008-12-02
Singh, Ramnandan (Department: 2614)
Multiplex communications
Duplex
Transmit/receive interaction control
Reexamination Certificate
active
07460499
ABSTRACT:
An on-chip reduced complexity modulation noise estimation mechanism for performing nonlinear signal processing to analyze modulation noise to determine whether a semiconductor device under test complies with the performance criteria set by specifications or a standard corresponding thereto. When used in a two-point transmitter modulation architecture, the mechanism relies on the fact that the noise statistics at the output of the transmitter can be determined by observing the phase error output of the phase detector within the phase locked loop. In the digital embodiment of the mechanism, the phase error signal is compared to a configurable threshold value to generate an exception event. If the number of exception events exceeds a configurable max_fail value after comparisons of a configurable number of phase error samples, the test fails. A pass/fail signal is output reflecting the result of the test. The test comprises a configurable number of test samples to permit flexibility in the tradeoff between the time required to complete the test versus the statistical reliability of the test result, i.e. the probability of it correctly determining whether the tested device complies with target specifications.
REFERENCES:
patent: 5754437 (1998-05-01), Blazo
patent: 5883930 (1999-03-01), Fukushi
patent: 6181258 (2001-01-01), Summers et al.
patent: 6603821 (2003-08-01), Doi
patent: 6665339 (2003-12-01), Adams et al.
patent: 6714605 (2004-03-01), Sugar et al.
patent: 6963629 (2005-11-01), Boerstler et al.
patent: 7046792 (2006-05-01), Harrow et al.
patent: 7203229 (2007-04-01), Ishida et al.
Sakuta et al, “Measurement of Phase Noise in High Performance Oscillator Using PLL-type Frequency Multiplier”, Electronics and Communications in Japan, Part 2, vol. 84, No. 8, 2001, pp. 64-70.
Y. Sakinori, H. Mino, Y. Sekine, “Measurement of Phase Noise in High-Precision Oscillator Using PLL-Type Frequency Multiplier”, Electronics and Communications in Japan, Part 2, vol. 84, No. 8, pp. 64-70, 2001.
M. Takamiya, H. Inohara, M. Mizuno, “On-Chip Jitter-Spectrum-Analyzer for High-Speed Digital Designs”, International Solid State Circuits Conf. (ISSCC) 2004.
Eliezer Oren
Friedman Ofer
Staszewski Bogdan
Brady III Wade James
Neerings Ronald O.
Singh Ramnandan
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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