Pulse or digital communications – Pulse position – frequency – or spacing modulation
Reexamination Certificate
1998-07-01
2002-08-27
Pham, Chi (Department: 2631)
Pulse or digital communications
Pulse position, frequency, or spacing modulation
C329S313000
Reexamination Certificate
active
06442200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a modulating circuit, a demodulating circuit and a modulating and demodulating circuit system, using a PPM method.
2. Descriptions of the Related Art
Conventionally, a modulation method, called PPM (Pulse Position Modulation) method has, been known. In this modulation method, a series of data is divided wherein a predetermined number of bits are used as a unit. Then, each division of data is converted into a PPM signal in accordance with a predetermined conversion rule. The PPM signal represents each division of data as a position of a carrier pulse provided in a unit period called ‘symbol period’. The carrier pulse is provided in the symbol period at any one of N chips which are obtained as a result of dividing the symbol period by N. The modulation method in which the symbol period is divided by N is called ‘N-value PPM method’. For example, in the method of the IrDA 1.1 (“Infrared Data Association Serial Infrared (SIR) Physical Layer Link Specification”, version 1.1, 1995), 4 Mbps, a 4-value PPM method is used.
(The IrDA (Infrared Data Association) is the association whose purpose is to create infrared serial data interconnection standards. More than 120 companies throughout the world participate in the IrDA. Many IrDA members are now developing and manufacturing their IrDA compliant product.)
FIG. 1
shows the PPM signal which is obtained as a result of a data signal undergoing the modulation in the 4-value PPM method. In the 4-value PPM method, a data signal is divided so that 2 bits are one unit. Then, each 2 bits of the data signal are converted into the PPM signal as a result of a pulse being provided at a chip specified in accordance with the value of the 2 bits of the data signal. For purpose of convenience, the 4 chips in one symbol period are represented as chip
1
, chip
2
, chip
3
and chip
4
in chronological order. In accordance with a predetermined conversion rule, the 2 bits of data signal “00” are converted into the PPM signal “1000” wherein the pulse is provided at the chip
1
. The 2 bits of data signal “10” are converted into the PPM signal “0100” wherein the pulse is provided at the chip
2
. The 2 bits of data signal “01” are converted into the PPM signal “0010” wherein the pulse is provided at the chip
3
. The 2 bits of data signal “11” are converted into the PPM signal “0001” wherein the pulse is provided at the chip
4
.
Demodulation of the thus-obtained PPM signal is performed by using a clock signal having a frequency several times the transmission rate of the PPM signal. In the demodulation, the position of the carrier pulse, that is, the timing of the chip at which the pulse is provided, is detected. Then, by using the detected timing of the chip, the original data is obtained based on the conversion rule which was used in the modulation.
FIG. 2
shows a demodulating circuit of the transmission rate of 4 Mbps in the related art. This demodulating circuit demodulates the PPM signal obtained through the 4-value PPM method so as to obtain the original data signal. This circuit includes a flip-flop
1
, a shift register
2
, a register
3
, a decoder
4
, a counter
5
, an inverter
6
and an OR gate
7
.
A clock signal having the frequency of 8 MHz which is perfectly in synchronization with the PPM signal is input to the flip-flop
1
. In this circuit, the level of the PPM signal is determined at each decaying edge of the clock signal of 8 MHz. Thus, data for each 4 bits is obtained, and the original data is obtained therefrom through the decoder
4
. The data input to the flip-flop
1
is output to the subsequent shift register
2
in synchronization with the timing of each decaying edge of the clock signal (See a time chart shown in FIG.
3
).
The shift register
2
performs digital-to-parallel conversion on the thus-provided data, and outputs a 4-bit parallel signal from respective output terminals Q
1
, Q
2
, Q
3
and Q
4
in response to inputting of the clock signal. This 4-bit parallel signal (Q
1
, Q
2
, Q
3
and Q
4
) is input to data inputting terminals D
0
, D
1
, D
2
and D
3
of the register
3
in synchronization with the clock signal, respectively.
The counter
15
is a 2-bit counter, and the count value thereof is incremented in synchronization with each decaying edge of the clock signal. The signals output from output terminals Q
0
and Q
1
of the counter
5
are input to two inputting terminals of the 3-input OR gate
7
, respectively. The clock signal is inverted by the inverter
6
and the thus-obtained clock signal is input to the remaining input terminal of the 3-input OR gate
7
. In response to these signals input to the 3-input OR gate
7
, the OR gate
7
outputs a clock pulse of “L” to the register
3
in synchronization with the rising edge of the first cycle of the clock signal.
The shift register
3
outputs the 4-bit parallel signal (Q
1
, Q
2
, Q
3
and Q
4
), which has been output from the shift register
2
, to the decoder
4
at the timing at which a clock pulse of “H”, output from the OR gate
7
, is input to the shift register
3
.
The decoder
4
demodulates the 4-bit parallel signal which has been input to input terminals I
0
, I
1
, I
2
and I
3
thereof based on the predetermined conversion rule so as to obtain and output the 2-bit data signal which is the signal before having been modulated. Through the decoder
4
, the PPM signal “1000” is converted into the 2-bit data signal “00”, the PPM signal “0100” is converted into the 2-bit data signal “10”, the PPM signal “0010” is converted into the 2-bit data signal “01”, and the PPM signal “0001” is converted into the 2-bit data signal “11”.
For example, in the method of the IrDA1.1, 4 Mbps, the span of one chip (pulse) is 125 ns. In this case, in order to determine the position of the carrier pulse, a clock signal having a frequency of equal to or more than 8 MHz is required. During the demodulation, this clock signal is input to the flip-flop
1
, shift register
2
, counter
5
and so forth at any time. As a result, a large amount of electric current is consumed by the demodulating circuit.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a modulating circuit, a demodulating circuit and a modulating and demodulating circuit system, using the PPM method, by which a reduced amount of electric current is consumed.
A first demodulating circuit, according to the present invention is provided for demodulating a PPM signal obtained as a result of modulation performed in accordance with a PPM method. The circuit comprises:
a detecting circuit detecting a predetermined carrier pulse provided within a symbol period of the PPM signal, using a clock signal having a frequency doubler or higher than double the transmission rate of the PPM signal.
Controlling means is provided for stopping supply of the clock signal to thee detecting circuit after the detecting circuit detects the predetermined carrier pulse until the subsequent symbol period starts.
A first modulating circuit, according to the present invention, is provided for modulating an input data signal into a PPM signal in accordance with a PPM method. The circuit comprises
counting means for dividing a predetermined amount of the input data signal into divisions, each division having a predetermined number of bits, and counting an appearance frequency of the divisions of the input data signal for each identical data.
Setting means is provided for setting, in accordance with the appearance frequency of the divisions of the input data signal counted for each identical data by the counting means, a conversion rule in accordance with which the divisions of the input data signal are converted into the PPM signal for each identical data.
Modulating means is provided for modulating the predetermined amount of the input data signal into the PPM signal in accordance with the conversion rule set by the setting means; and
Outputting means is provided for outputting data of the conversion rule and the PPM signal.
Burd Kevin M.
Cooper & Dunham LLP
Pham Chi
Ricoh & Company, Ltd.
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