Modularized scan path for serially tested logic circuit

Details Modularized scan path for serially tested logic circuit Modularized scan path for serially tested logic circuit

1985-10-23

1987-10-20

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

047019212

ABSTRACT:
A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) provides data to a serial input to each of the modules (26). The serial output of each of the modules (26) is interfaced with a scan data out line (30). An address on a bus (16) is provided to a decoder (52) to select one of the modules (26). An isolation gate (48) allows for input of data to only the select one of the modules (26) and an isolation gate (50) allows output of data only from the select one of the modules (26) to the scan data out line (30).

REFERENCES:
patent: 4441075 (1984-04-01), McMahon
patent: 4503537 (1985-03-01), McAnney
patent: 4519078 (1985-05-01), Komonytsky
patent: 4534028 (1985-08-01), Trischler
patent: 4580137 (1986-04-01), Fiedler et al.
patent: 4597042 (1986-06-01), d'Angeac et al.
Generalized Scan Test Technique for VLSI Circuits, IBM Technical Disclosure Bulletin, vol. 28, No. 4, Sep. 1985, pp. 1600-1604.

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