Modularized architecture for rendering scaled discrete cosine tr

Details Modularized architecture for rendering scaled discrete cosine tr Modularized architecture for rendering scaled discrete cosine tr

1996-04-15

1997-07-15

Herndon, Heather R.

Boots, shoes, and leggings

36472502, G06T 120

Patent

active

056490771

ABSTRACT:
The present invention describes a circuit for performing high speed forward Scaled Discrete Cosine Transform (SDCT) and inverse Scaled Discrete Cosine Transform (ISDCT) in pipeline architecture which is ideally, but not exclusively, used for compressing and decompressing large volume image data in real time. A high throughput of image data transform and inverse transform is achieved with a relatively slow internal clock. The four stage pipeline architecture of the present invention requires no more than five multipliers in rendering either the forward SDCT or inverse SDCT coefficients. The lower-order SDCT's for either the forward or the inverse direction are imbedded in the higher-order forward SDCT or inverse SDCT respectively. By taking advantage of the recursive properties of the SDCT's, a larger size SDCT can be always implemented by using a combination of variants of smaller size SDCT. The scaling effects of the coefficients is restored as the compressed image data undergoes the inverse quantization stage.

REFERENCES:
H.S. Hou, "A Fast Recursive Algorithm For Computing the Discrete Cosine Transform," IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-35, No. 10, pp. 1455-1461. Oct. 1987.
H.S. Hou, "Resursive Scaled-DCT," SPIE vol. 1567 Applications of Digital Image Processing XIV, pp. 402-412 1991.
Linzer, et al, "New Scaled DCT Algorithms for Fused Multiply/Add Architectures", ICASSP '91: Acoustics, Speech & Signal Processing Conference, pp. 2201-2204 1991.
Wang, et al, "Highly Parallel VLSI Architectures for the 2-D DCT and IDCT Computations", TENCON '94, IEEE Region 10 Conference, pp. 295-298 1994.

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