Modular memory employing varying number of imput shift register

Static information storage and retrieval – Magnetic bubbles – Guide structure

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365221, 365 78, 364DIG1, G06F 1300, G06F 1200

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051758326

ABSTRACT:
A memory including several modules with each module receiving at the input requests coming from a processor and furnishing at the output the responses to these requests. The requests are transmitted to the input of each module via an input shift register. The responses coming from a module are transmitted to the input of a processor via an output shift register. The number of stages of the input shift register is different for each of the modules and the total number of stages for the input and output shift registers associated with one of the modules is constant and independent of the module in question.

REFERENCES:
patent: 3566363 (1971-02-01), Driscoll et al.
patent: 4156288 (1979-05-01), Spandorfer
patent: 4809232 (1989-02-01), Baumbaugh et al.
patent: 4899310 (1990-02-01), Baba et al.
patent: 4918600 (1990-04-01), Harper, III et al.
IEEE Proceedings on the 4th Annual Symposium on Computer Architecture, Mar. 23-25, 1977, pp. 90-94, IEEE, New York, U.S.; S. R. Ahuja et al.: "A modular memory scheme for array processing", col. 3, lines 37-74; FIGS. 1, 6.

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