Modular chip select control circuit and method for performing pi

Details Modular chip select control circuit and method for performing pi Modular chip select control circuit and method for performing pi

1994-08-31

1997-04-01

Lane, Jack A.

Static information storage and retrieval

Magnetic bubbles

Guide structure

36523006, 3642318, G06F 1312

Patent

active

056175590

ABSTRACT:
A modular chip select control circuit (80) is scalable by having an address decode stage (90) with a first number of address decoders, a control stage (100) with a second number of control units, and a pin configuration stage (110) with a third number of pin configuration logic circuits. These three numbers, defining the number of memory regions, the access pipeline depth, and the number of chip select signals, respectively, are independent and may be changed between chip designs to accommodate different system needs. The control stage includes an early pipeline control circuit (186) which allows the control units (170, 180) to pipeline pending memory cycles, based on an accessed region's characteristics. The early pipeline control circuit (186) together with the control units (170, 180) enforce a set of pipelining rules to ensure data integrity and proper cycle termination, thus providing an efficient series of pipelined memory access cycles.

REFERENCES:
patent: 4670748 (1987-06-01), Williams
patent: 5111423 (1992-05-01), Kopec, Jr. et al.
patent: 5151986 (1992-09-01), Langan et al.
patent: 5359717 (1994-10-01), Bowles et al.
patent: 5469544 (1995-11-01), Aatresh et al.
MC68332 User's Manual, (System Integration Module), Motorola, Inc., 1990, pp. 4-27 through 4-46.

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