Boots – shoes – and leggings
Patent
1995-11-06
1997-12-23
Bowler, Alyssa H.
Boots, shoes, and leggings
395800, 395670, 395672, 3642813, 364281, G06F 1516, G06F 940
Patent
active
057014825
ABSTRACT:
A modular array processor architecture (10) comprising a plurality of interconnected parallel processing node (11)s that each comprise a control processor (12), an arithmetic processor (13) having an input port (22) for receiving data from an external source that is to be processed, a node memory (14) that also comprises a portion of a distributed global memory, and a network interface (15) coupled between the control processor (12), the arithmetic processor (13), and the node memory (14). Data and control buses (17, 18) are coupled between the arithmetic processors (13) and network interfaces (14) of each of the processing nodes (11). Respective network interfaces (15) link each of the arithmetic processors (13), node memories (14) and control processors (12) together to provide for communication throughout the architecture (10) and permit each node to communicate with the node memories (14) of all other processing nodes (11). This linking, along with the use of a heuristic scheduling algorithm, provides for load balancing between the processing nodes (11). Data queues are segmented and distributed across the architecture (10) in a way that the source and destination nodes (11) process data locally in the memory (14), while overflow is kept in distributed bulk memories (14). The network interfaces (15) buffer data transferred over the data and control buses (17, 18) to a respective node (11). Also, the network interfaces (15) operate as high-speed DMA controllers to transfer data between the arithmetic processor (13) and node memory (14) of a processing node (11) independent of the operation of the control processor (12) in that node (11). The control bus (17) is used to keep track of available resources throughout the architecture (10) under control of a heuristic scheduling algorithm that reallocates tasks to available arithmetic processors (13) based on a set of heuristic rules to achieve the load balancing. The data bus (18) is used to transfer data between the node memories (14) so that reallocated tasks are performed by selected arithmetic and control processors (13, 12) using data that is stored locally.
REFERENCES:
patent: 4577272 (1986-03-01), Ballew et al.
patent: 4654654 (1987-03-01), Butler et al.
patent: 4839798 (1989-06-01), Eguchi et al.
patent: 5031089 (1991-07-01), Liu et al.
patent: 5155858 (1992-10-01), DeBruler et al.
patent: 5283897 (1994-02-01), Georgiadis et al.
patent: 5357632 (1994-10-01), Pian et al.
patent: 5392429 (1995-02-01), Agrawal et al.
patent: 5459864 (1995-10-01), Brent et al.
Xu et al., "Dynamic Load Balancing for Parallel Program Execution on a Message-Passing Multicomputer", IEEE, Dec. 1990, pp. 402-406.
Sarje et al., "Heuristic model for task allocation in distributed computer systems", IEE Proceedings, Sep. 1991, pp. 313-318.
Davies Steven P.
Harrison R. Loyd
Bowler Alyssa H.
Davis Walter D.
Denson-Low W. Kay
Grunebach G. S.
Hughes Aircraft Company
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