Boots – shoes – and leggings
Patent
1984-07-12
1987-03-03
Thomas, James D.
Boots, shoes, and leggings
G06F 1318
Patent
active
046480650
ABSTRACT:
In an n-wide (n nominally equals 4) snapshot priority network apparatus the access of n+1 requestors to a memory unit is prioritized. Two requestors--the lowest priority one of normal system requestors called instruction processors plus a maintenance exerciser type requestor--share a single memory port which is nominally the lowest priority one of n such prioritized ports. Requests from both requestors are both honored upon a single priority snap, the instruction processor request nominally proceeding before the maintenance processor request. Although the n-wide priority network remains generally faster than any (n+1)-wide priority network, the maintenance exerciser type requestor is expediently serviced and cannot be locked out of access to memory by the competing higher priority requests of the instruction processor.
REFERENCES:
patent: 4493036 (1985-01-01), Boudreau et al.
Trost John R.
Zenk Daniel K.
Johnson Charles A.
Marhoefer Lawrence J.
Sperry Corporation
Thomas James D.
Ure Michael J.
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