Modified silicon CMOS process having selectively deposited Si/Si

Details Modified silicon CMOS process having selectively deposited Si/Si Modified silicon CMOS process having selectively deposited Si/Si

1992-05-27

1993-12-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437131, 437 45, 148DIG82, H01L 2170

Patent

active

052683249

ABSTRACT:
A process is disclosed for making CMOS devices with enhanced performance PMOS FETS by integrating germanium technology into a silicon-based fabrication method. Silicon-germanium layers are selectively grown on the surfaces of oxide-isolated PFET pockets of a silicon substrate previously prepared by a conventional silicon CMOS process. A silicon cap is deposited over each Si--Ge layer and gate insulator is formed over the cap provide gate dielectric for the PFETS. Gate insulator is formed over the NFET pockets to provide gate dielectric for the NFETS. Gate structures are completed along with source and drain junctions in accordance with normal practice. Provision also is made for the additional selective growth of a second silicon-germanium layer on the surfaces of oxide-isolated NFET pockets on the same CMOS substrate to enhance the performance of the NFETS as well as that of the PFETS.

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