Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-06-22
2001-03-20
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C438S448000
Reexamination Certificate
active
06204547
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to a method and structure for isolating devices such as metal oxide silicon (MOS) field effect transistors, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as bipolar transistors, complementary metal oxide semiconductor (CMOS) field effect transistors, bipolar complementary metal oxide semiconductor (BiCMOS) field effect transistors, among others.
Industry utilizes or has proposed techniques for isolating devices in an integrated circuit device. An example of a technique is the local oxidation of silicon (LOCOS) as defined in U.S. Pat. No. 3,970,486, assigned to U.S. Philips Corp. The LOCOS technique generally includes steps of forming a thin silicon dioxide layer (SiO
2
) (or pad oxide layer) overlying a silicon substrate. A layer of silicon nitride is formed overlying the silicon dioxide layer. A step of patterning the silicon nitride (Si
3
N
4
) layer to expose portions of the pad oxide is performed. The exposed portions of the pad oxide define regions for field isolation oxide. Using the silicon nitride as a mask, a step of thermal oxidation forms field isolation oxide regions in the exposed pad oxide regions.
A limitation with the LOCOS technique is certain undesirable effects caused by lateral oxidation of silicon dioxide occurs as illustrated by FIG.
1
. In particular, the lateral oxidation of silicon dioxide often causes an undesirable “bird's beak” type structure. As shown,
FIG. 1
illustrates a conventional field isolation oxide structure
10
including a semiconductor substrate
11
, a field isolation oxide region
13
, an active region
17
, and a bird's beak type structure
15
. As shown, the bird's beak type structure prevents formation of devices in active regions because of thickness
19
.
Various techniques have been proposed to overcome the undesirable effects of the bird's beak type structure. In particular, formation of a thinner oxide layer often creates a shorter bird's beak length. A thicker nitride layer also creates a shorter bird's beak length. But such techniques induce more crystal defects to the silicon substrate or the like. The crystalline defects increase resistance in the substrate, thereby causing switching problems or the like. The thinner bird's beak type structure also causes electrical current leakage between adjacent devices, by not effectively isolating such devices.
Another technique has been proposed to provide a thicker oxide layer to create a thicker bird's beak type structure. The thicker bird's beak type structure tends to prevent electric leakage between devices. But the thicker bird's beak type structure causes a longer bird's beak, that is, a bird's beak which protrudes further into the active device region. The longer bird's beak structure also reduces packing density of integrated circuits, which is clearly an undesirable result.
Still another technique uses a “poly-buffered” LOCOS method. The poly-buffered LOCOS method relies upon a multi-layered sandwich structure including an oxide layer, a polysilicon layer, and a nitride layer. The poly-buffered LOCOS method reduces lateral encroachment of silicon dioxide. But the poly-buffered LOCOS method creates a second bird's beak type structure as illustrated by FIG.
2
. As shown,
FIG. 2
illustrates conventional field isolation oxide regions
20
made by way of the conventional poly-buffered LOCOS method. The conventional method provides a semiconductor substrate field isolation oxide regions
23
, a first bird's beak type structure
25
, and a second bird's beak type structure
29
. Another limitation with the poly-buffered LOCOS method includes polysilicon etching residues
27
remaining on edges of the field isolation oxide regions. The second bird's beak type structure and etching residues are clearly undesirable results.
From the above it is seen that a method of fabricating a semiconductor isolation region that is easy, cost effective, and reliable is often desired.
SUMMARY OF THE INVENTION
The present invention provides an improved method and resulting integrated circuit device structure. The present field isolation oxide region fabrication method provides a relatively consistent and easy to fabricate structure, with substantially no bird's beak type structures.
In a specific embodiment, the present invention provides a method of forming a semiconductor integrated circuit. The present method includes the steps of providing a semiconductor substrate with a top surface. The present method also includes forming a pad oxide layer overlying the top surface, forming a polysilicon layer overlying the pad oxide layer, and forming a second silicon nitride layer overlying the silicon nitride layer. The second silicon nitride layer is much thicker than the first layer of silicon nitride. A step of patterning the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer to define a mask is also provided. The mask includes exposed regions of the pad oxide layer.
An alternative embodiment provides a semiconductor substrate with a top surface. The present embodiment also includes an oxide layer overlying the top surface, a polysilicon layer overlying the oxide layer. A first silicon nitride layer is overlying the polysilicon nitride layer, and a second silicon nitride layer is overlying the first silicon nitride layer. The second silicon nitride layer is much thicker than the first layer of silicon nitride. In the embodiment provided, the second silicon nitride layer, the first silicon nitride layer, and the polysilicon layer define a mask. The mask includes exposed regions of the pad oxide layer.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
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patent: 5192707 (1993-03-01), Hodges et al.
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patent: 4-249324 (1992-04-01), None
Guidi, R.L. et al., “Characteristics of Poly-Buffered LOCOS in Manufacturing Environment,” 1989,J. Electrical Soc., vol. 136, No. 12, pp. 3815-3820.
Chaudhuri Olik
Duy Mai Anh
Mosel Vitelic Inc.
Townsend and Townsend / and Crew LLP
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