Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-08-07
2001-05-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06228736
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory (DRAM) devices, and more particularly to a method for fabricating cylinder-shaped stacked capacitors for DRAM cells using an improved semiconductor process. This process eliminates erosion of the insulating layer over the devices on the substrate when misaligned openings in an overlying disposable silicon oxide layer are used as a template for making the DRAM capacitor bottom electrodes.
(2) Description of the Prior Art
Ultra Large Scale Integration (ULSI) technologies have dramatically increased the circuit density on the semiconductor chip. This increase in density is due in part to advances in high-resolution photolithography and anisotropic plasma etching in which the directional ion etching results in essentially bias-free replication of the photoresist image in the underlying patterned layers, such as in polysilicon and insulating oxide layers and the like.
One such circuit type where this high-resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuits consist of an array of individual memory cells, each cell consisting of an access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the chip.
One conventional method to achieve a high density of memory cells on a DRAM chip is to form a capacitor node contact to one of the source/drain areas of the FET in each of the memory cells, and then to form a bottom electrode aligned over the node contact. In future technologies having minimum feature sizes less than 0.25 micrometers, misalignment of the bottom electrode to the node contact can result in processing and reliability problems. This problem is best illustrated in
FIGS. 1A through 3B
for this conventional method.
FIG. 1A
shows a typical memory cell area on a substrate
10
having a silicon oxide (SiO
2
) first insulating layer
12
and a silicon nitride (Si
3
N
4
) etch-stop layer
14
. A patterned photoresist mask (not shown) and plasma etching are used to etch first openings
1
in layers
14
and
12
for node contacts. A doped first polysilicon layer is deposited and etched back to form the node contact
18
in opening
1
. Because of variations in etching conditions and non-uniformities across the substrate, the node contacts
18
can be overetched thereby exposing the sidewalls of the first insulating layer
12
. A disposable second insulating layer
22
is deposited, and a second photoresist mask
24
and plasma etching are used to etch second openings in layer
22
for forming the capacitor bottom electrode, as shown in FIG.
1
A. However, because of the difficulty of aligning the images for high-density circuits, the photoresist
24
for making the second opening
2
can be misaligned to the node contact
18
, as shown in FIG.
1
B.
Referring to
FIGS. 2A and 2B
, a conformal second polysilicon layer is deposited and polished back to form the bottom electrode
26
, and as shown in
FIG. 3A
the disposable SiO
2
second insulating layer
22
is removed using a wet etch in a hydrofluoric acid solution. The Si
3
N
4
etch-stop layer
14
prevents the etchant from attacking the first insulating layer
12
over the devices on the substrate. However, as shown in
FIG. 3B
for the misaligned opening
2
for the bottom electrode, when the second insulating layer
22
is etched, the first insulating layer
12
is also etched or eroded away at the point A, which can cause electrical shorts and other reliability problems. Therefore, it is desirable to modify the conventional method to prevent this oxide erosion problem.
There are numerous methods of making DRAM circuits with stacked capacitors that are reported in the literature. Several methods for making DRAM capacitors are described by Fazan et al., in U.S. Pat. No. 5,597,756, by Matthews et al., in U.S. Pat. No. 5,354,705, by Jones et al., in U.S. Pat. No. 5,405,796, and by Linliu et al., in U.S. Pat. No. 5,688,713.
However, none of the cited patent references explicitly addresses the problems associated with misalignment and erosion of the oxide. Therefore, there is still a need to improve upon the conventional method for fabricating reliable DRAM capacitors on memory cells.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide a method for making memory cells on DRAM devices with improved cylinder-shaped stacked capacitors having increased capacitance.
It is another object of this invention to provide a more controllable etch process using a protective silicon nitride (Si
3
N
4
) layer having sidewall spacers. This layer prevents erosion of an underlying silicon oxide (SiO
2
) over the devices on the substrate when a disposable overlying SiO
2
layer, used to form the capacitor, is removed in a wet etch.
Still another object of this invention is to provide a cost-effective manufacturing process.
The invention begins by providing a semiconductor substrate (wafer) composed of single crystalline silicon. The details for the semiconductor devices in the substrate are not explicitly described in detail since they are not essential to understanding the invention. But typically the memory cells on a substrate for DRAM circuits have device areas surrounded and electrically isolated by field oxide (FOX) regions and semiconductor devices such as field effect transistors (FETs) in the device areas. A storage capacitor is then formed over each of the memory cell areas to one of the device contact areas using a polysilicon plug as the node contact.
Continuing with the process, the method for making these improved cylinder shaped capacitors using this modified method to avoid silicon oxide erosion when misalignment of the capacitor to the polysilicon plug (node contact) occurs is described. A first insulating layer is deposited on the substrate, which is then planarized. The first insulating layer is a silicon oxide (SiO
2
) or a doped oxide such as a borophosphosilicate glass (BPSG). A first etch-stop layer, preferably composed of silicon nitride (Si
3
N
4
), is then deposited on the first insulating layer. First openings are selectively etched for capacitor node contacts in the first etch-stop layer and in the first insulating layer to the device areas. A conductively doped first polysilicon layer is deposited to fill the first openings, and is etched back to form polysilicon plugs in the first openings. Unfortunately, it is difficult to consistently etch back the polysilicon because of run-to-run process variations, and because of etch non-uniformity across the wafer. This overetching can cause erosion of the SiO
2
first insulating layer in subsequent steps if and when misalignment occurs. By the method of this invention, a second etch-stop layer is deposited and is etched back to form sidewall spacers that protect the exposed first insulating layer at the sidewalls in the first openings in which the first polysilicon layer is overetched. A second insulating layer is deposited on the first etch-stop layer and over the sidewall spacers formed from the second etch-stop layer and over the polysilicon plugs. Second openings are selectively etched, aligned over and wider than the first openings, in the second insulating layer. The second openings are etched to the first etch-stop layer and to the polysilicon plugs. However, because of the more critical design rules for alignment, misalignment of the second opening to the first opening can occur, and in the conventional process without etch-stop sidewall spacers can result in erosion of the first insulating layer during later processing steps. Next a conformal second polysilicon layer is deposited over and in the second opening
Lee Yu-Hua
Wu James
Ackerman Stephen B.
Hoang Quoc
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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