Modified four transistor EEPROM cell

Details Modified four transistor EEPROM cell Modified four transistor EEPROM cell

1985-09-09

1987-09-22

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365104, G11C 1134

Patent

active

046959793

ABSTRACT:
An electrically erasable programmable memory cell of the four transistor type in which a floating gate transistor has one end of its source to drain path coupled to the write line and the other end to the read line through a read switch. Its control gate is connected to the sense line. A tunnel device has a cathode connected to the floating gate of the floating gate transistor, and an anode through a write switch connected to the write line. The gates of both the read and write select transistors are connected to the row line. By coupling one end of the read switch to the read line rather than connecting one end of the source to drain path of the floating gate transistor to the read line for unselected cells in which the read switch is off, only the capacitance of one end of the read switch is added to the parasitic capacitance of the read line whether the floating gate of the floating gate transistor has previously been charged negatively or positively. Thus, the precharging time of the read line will be independent of the programmed condition of the cell and will result in an access time that is as fast or faster for either programmed condition than previously attainable.

REFERENCES:
patent: 4402064 (1983-08-01), Arakawa
patent: 4628487 (1986-12-01), Smayling

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