Modified and robust self-aligning contact process

Details Modified and robust self-aligning contact process Modified and robust self-aligning contact process

1992-08-11

1994-02-15

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 47, 437 60, 437913, 437919, H01L 2182

Patent

active

052866670

ABSTRACT:
The method is described for fabricating an integrated circuit having a combination of a capacitor and metal oxide semiconductor field effect transistor with gate electrodes and source/drain regions. The method features the use of silicon nitride or silicon oxynitride barrier layers. The barrier layer is a key to the successful lightly doped drain spacer etch process. The barrier layer aids in endpoint detection for the plasma etch. This allows for less loss of the field oxide and greater thickness control of the field oxide regions. Further, the silicon nitride endpoint detection allows for the removal of undesirable residual silicon oxide from the surface of the capacitor plate without loss of the polysilicon capacitor plate itself.

REFERENCES:
patent: 4183040 (1980-01-01), Rideout
patent: 4704368 (1987-11-01), Goth et al.
patent: 4990980 (1991-02-01), Wada
patent: 5001078 (1991-03-01), Wada

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