Modification of timing in an emulator circuit and method

Details Modification of timing in an emulator circuit and method Modification of timing in an emulator circuit and method

1995-02-28

1997-10-14

Teska, Kevin J.

395309, G06F 944, G06F 1342

Patent

active

056780303

ABSTRACT:
An emulator circuit and method of emulating operation of a computer system in which the emulator circuit may be selectively operated with memory devices that require coincident availability of data and address information during a clock cycle, and with systems that require data and address information at different times during the clock cycle. (Address information including address signals for selecting memory locations and memory control signals.) The circuit includes a data bus port for receiving data that has a transition during a clock cycle, plural address lines, each for communicating address information that has a transition during the clock cycle, an address latch control (ALC) switch with a buffer for each of the address lines, each address buffer having a latch with a first position wherein the data transition and address information transition occur at the same time during a clock cycle, and a second position wherein the address information transition leads the data transition by about one-half clock cycle, and a logical gate for receiving an ALC signal that indicates whether the first position or the second position is selected.

REFERENCES:
patent: 4641261 (1987-02-01), Dwyer et al.
patent: 4975593 (1990-12-01), Kurakazu et al.
patent: 5307469 (1994-04-01), Mann
patent: 5359717 (1994-10-01), Bowles et al.
Computer Dictionary, Microsoft Press, Second Edition, 1994. (p. 265).

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