Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-09-22
2004-02-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S598000, C438S612000, C361S760000
Reexamination Certificate
active
06689634
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit devices. More specifically, the present invention relates to a modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (ball grid array (BGA) or land grid array (LGA)) package to increase the routability of the package substrate and increase the device reliability.
BACKGROUND OF THE INVENTION
The parallel drive towards total cost reduction and miniaturization has, in recent years, given rise to an increasing emphasis on very small IC package solutions. This is particularly evident in consumer based end equipment such as camcorders and mobile telephone handsets. Despite a formal definition, packages whose area is similar to that of the IC they encapsulate are loosely referred to as chip scale packages (CSPs).
CSPs are in many ways an ideal solution to the cost reduction and miniaturization requirement. They offer enormous area reductions compared with quad flat package, and have increasing potential to do so without adding system level cost. In the best case, CSPs are able to compete today, on a cost per terminal basis, with quad flat packages. For example, various CSPs from Texas Instruments are now available at cost parity with thin quad flat packages.
Texas Instruments produces a polyimide-based family of CSPs known as MicroStarBGA™ (see FIG.
1
). This CSP
10
, like most others, uses solder alloy balls
12
as the interconnection between the package substrate
14
and the board on which the packages is soldered. As with all such packages, the solder balls formed between the package and the board are susceptible to fatigue when exposed to cyclic ambient temperature conditions.
JEDEC and EIAJ are increasingly documenting fine pitch BGA industry standards. The finest pitch standard that is currently widely recognized is 0.50 mm pitch. However, broad acceptance and use of 0.50 mm pitch CSPs is still very limited, due to the following reasons:
1) Lack of package availability from a broad range of suppliers.
2) Lack of package reliability data, and concerns that reliability will not meet the requirements of even the consumer markets.
3) The printed circuit board (PCB) requirements for mounting such fine pitch packages are very demanding. There is limited availability of such boards, and in many cases, the higher PCB cost is prohibitive.
4) Lack of experience on the part of most SMT assembly operations in manufacturing with such fine pitch BGAs.
5) Belief that 0.50 mm pitch CSP component cost is inherently higher, on a cost per terminal basis, than for example, 0.80 mm pitch CSPs.
Clearly, key to the successful adoption of a package that has to meet the twin goals of system cost reduction and miniaturization, is the package reliability. As the ball pitch shrinks, it becomes more and more difficult to meet reliability specifications, due to the ball joint fatigue phenomenon mentioned in the introduction. Both the size (volume) and shape of the solder ball influence reliability. The weakest link in the system is normally the point of smallest cross-section in the solder joint, which is via (
28
), as seen in FIG.
2
.
Thus a major challenge in the design of the CSP substrate is to optimize the diameter of this solder via. However, as the ball density on the package increases (more balls on more rows, at finer pitch), substrate routing density also increases, often leading to a package design of inherent lower reliability. To demonstrate this, the current optimum design for reliability, as shown in
FIG. 3
, is:
Ball (12) pitch
500 um
Line (30)/Space
28/42 um
Via (32) diameter
280 um
Solder ball pad (34) diameter
380 um
NB pad size is via size + 100 um.
These optimum rules, based on design for reliability, allow only one trace or line (
30
) to pass between adjacent balls (
12
). This is important since in CSP packages, since a line or trace (
30
) must extend from each solder ball pad (
34
) to an exterior edge of the substrate (
14
) (e.g., to facilitate electrolytic plating). Such restriction of limiting one line or trace between adjacent balls will limit the total number of balls that may actually be implemented in a matrix type ball grid array since there will be a limitation on how many traces or lines may actually extend out to an exterior surface of the substrate.
FIG. 4
discloses a conventional ball footprint (regular pattern of 3 row of balls) having 144 balls (on a 0.5 mm pitch) on a 10×10 mm package body. To achieve this dense routing, a designer has to compromise. There are typically three options:
1) Tighten the line/space design rule for the connection traces. This can add cost or may be beyond the capability of the substrate technology. *
2) Reduce the via diameter. This will reduce the fatigue life of the solder joint.
3) Reduce the minimum overlap of the ball pad to via (see FIG.
4
). This has negative reliability implications, as it will effect the moisture sensitivity of the package.
* NB. The line/space design rules can be improved upon by reducing the copper film thickness. This will not be discussed since the principles explained here are applicable to enhance the package reliability for any given metal film thickness. The most common compromise, when faced with having to increase routing density, is to use the tightest line/space rule available for the given substrate technology, and then to reduce the ball via diameter. This is demonstrated in the example in
FIG. 5
, and is the design used for the footprint in FIG.
4
.
FIG. 5
discloses a routing pattern for
3
full rows of balls, in which:
Ball (12) pitch
500 um
Line (30)/Space
28/42 um
Via (32) diameter
218 um
Solder ball pad (34) diameter
318 um
Thus, in the case of
FIG. 4
(and by implication FIG.
5
), the designer chose option
2
. In order to allow two traces to route between adjacent balls, the via diameter had to be reduced from 280 um to 218 um, which is a violation of the optimum design rules which call for a via diameter of 280 um. There are significant reliability implications of such a modification or change, as is well known in the art.
SUMMARY OF THE INVENTION
A modeling technique for selectively depopulating solder contacts (and their respective contact pads, vias and traces or lines) from a conventional foot print of a grid array package (Ball Grid Array (BGA), or Land Grid Array (LGA)) to improve device reliability, and a BGA or LGA package so modeled. The modeling technique anticipates a routing of traces through the gap resulting from the depopulated solder contacts as additional space for routing traces or lines from solder contact pads to an exterior surface of a substrate (
14
) upon which a semiconductor die (
20
) is mounted. An advantage of the present invention is that it provides an easy to use modeling technique (e.g., in this case an Excel spreadsheet) that allows a user to easily predict whether or not a preselected number of balls on a specific body size device will be possible.
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Rozenblit et al., “Towards a VLSI Packaging Design Support Environment (PDSE); Concepts and Implementation”, IEEE International Conf. on Computer Design: VLSI in Comp. and Processors, Sep. 17-19, 1990, pp. 443-448.*
Blood et al., “Early Analysis of Chip Scale Package Design Trade-offs”, IEEE Symposium on IC/Package Design Integration, Feb. 2-3, 1998, pp. 64-69.*
Lindsey et al., “JACS-Pak/sup TM/ Flip-Chip Scale Package Development and Characterization”, 48th IEEE Electronic Components & Tech. Conf., May 2
Brady III Wade James
Malsawma Lex H.
Neerings Ronald O.
Smith Matthew
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