Modeling method of MOSFET

Details Modeling method of MOSFET Modeling method of MOSFET

1999-08-12

2001-06-12

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Electrical analog simulator

Of electrical device or system

C703S013000, C703S015000

Reexamination Certificate

active

06246973

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a modeling method of MOSFET (metal-oxide semiconductor field effect transistor).
BACKGROUND OF THE INVENTION
FIGS. 13 and 14
show a schematic plan view of a MOSFET and a cross-sectional view along I—I thereof to explain the structure of the MOSFET. In
FIG. 13
, reference numeral
11
denotes an active area;
12
denotes a gate electrode;
13
denotes a contact portion to a drain electrode in a drain region; and
14
denotes a contact portion to a source electrode in a source region. In the main cross-section (
FIG. 14
) along I—I that traverses the active region
11
along the gate electrode
12
, reference numerals
10
,
15
, and
16
denote a substrate, a gate oxide film, and field oxide film, respectively.
Normally, the field oxide film
16
is obtained by forming a heat-resistant nitride film, such as, for example, silicon nitride film, on the substrate, and, after the nitride film is patterned by photolithography to a desired geometry, thermally oxidizing the substrate
10
using the remaining nitride film as a mask. During thermal oxidation, a so-called bird's beak is formed in a region extending from the field oxide film
16
to the subsequently formed gate oxide film
15
; thus, the effective channel width related to the electrical characteristics of the resulting device, that is, the effective value We of channel width, is smaller than its design value on both sides of the gate oxide film
15
by &Dgr;W
1
/2, respectively, or by &Dgr;W
1
in total.
Typically, the electrical characteristic of the MOSFET is characterized (modeled) in advance, and then MOSFET-based integrated circuitry is designed by using the model. Conventionally, when the electrical characteristic of the MOSFET is modeled, Eq. (1) shown below is applied to the design value W of channel width in consideration of the above-mentioned bird's beak to determine the effective value We of channel width, which is used as a channel width.
We=W−
(&Dgr;
W
1
/2+&Dgr;
W
1
/2)=
W−&Dgr;W
1
  Eq. (1)
Eq. (1) indicates that the transistor gain of the MOSFET is zero until the design value W of channel width reaches a certain value, that is, &Dgr;W
1
; thus, it can be said that &Dgr;W
1
is an offset value for W. Here, &Dgr;W
1
is a fixed value in the MOSFET manufacturing process, and is handled as an independent parameter of the channel width design value W.
However, with the correction of the channel width due to Eq. (1) above, as the channel width becomes more scaled down, the above &Dgr;W
1
is not actually fixed, so there is a problem that a difference between the device characteristic predicted and the device characteristic resulting from actual fabrication is considerable.
Thus, for MOSFET modeling for a smaller channel width, a channel width correction equation, as shown in Eq. (2) below, has been proposed considering We varies according to the magnitude of the gate bias (Proc, IEEE Int. Conference on Microelectronic Test Structures, 133-137, Vol. 6, March 1993). Note that Gw (Vgs−Vth) in Eq. (2) represents a term that varies with the gate bias.
We=W+&Dgr;W+Gw
(
Vgs−Vth
)  Eq. (2)
By considering the dependency of the gate bias as shown in
FIG. 2
, correction can be made to some degree when the channel width is scaled down; however, there is a problem that modeling is complex and difficult. Additionally, when the channel width is scaled down, the final geometry is physically different than when the channel width is larger; the resulting influence is greater than the gate bias dependency.
It has also been proposed that a so-called Binning method be employed to correct the channel width. The Binning method involves dividing the W/L matrix into multiple areas according to the model fitting accuracy, where W and L are the design values of channel width and channel length, respectively, and performing characterization by use of Eq. (1) for each area, thereby achieving correction in greater detail according to the value of W/L.
With the Binning method, however, there are problems that if the value of W/L is on the boundary of the areas, it is unknown which modeling parameter should better be used, and handling of this case is inconvenient; it is difficult to assure continuity of models between areas; and all of the W/L values cannot be characterized (modeled) accurately. Furthermore, the modeling is complex.
Accordingly, it is an object of the present invention to provide a modeling method of MOSFET that can accurately and simply determine the effective value of channel width based on the design value of channel width when the channel width is scaled down, thereby accurately predicting the electrical characteristic of the MOSFET.
SUMMARY OF THE INVENTION
The present invention is implemented based on the finding that the error between the effective value We and design value W of channel width is due not only to &Dgr;W
1
but also to additional two factors. It is assumed here that the errors corresponding to those two factors are &Dgr;W
2
and &Dgr;W
3
, respectively. The effective value We of channel width is then given by Eq. (3) below.
We=W−&Dgr;W
1
+&Dgr;
W
2
+&Dgr;
W
3
  Eq. (3)
where &Dgr;W
1
is similar to the prior art, which is first described below. If the design value L of channel length is small, a value of &Dgr;W
3
occurs; as such, L is increased somewhat and set so that &Dgr;W
3
does not occur; the gate-to-source transistor gain is measured while varying the design value of channel width, thereby determining the relationship between W and transistor gain. If W is too small, &Dgr;W
2
occurs; as such, for values of W that are greater than that, the relationship between W and transistor gain is determined, thereby resulting in a linear regression line as shown in FIG.
2
. This linear regression line ramps up from a point that is offset from zero; when W is scaled down, the gate-to-source transistor gain is essentially zero. Thus, the value of W where the transistor gain starts to become an effective value greater than zero is regarded as &Dgr;W
1
.
Next, an explanation on &Dgr;W
2
is given. The length of the afore-described bird's beak, that is, the distance from the edge of the silicon nitride film
21
to the gate oxide film
15
, is longer (k
2
) as the channel width becomes wider as shown in
FIG. 3
(
b
), while it is shorter (k
1
) as the channel width becomes narrower as shown in
FIG. 3
(
a
) (P. U. Kenkare IEDM 1993,p479-482). In other words, as the channel width becomes smaller, the effective value We of channel width becomes longer. Typically, the geometry of the active area
11
near the gate region includes several types, as shown in
FIGS. 4
(
a
)-(
c
). For the type shown in
FIG. 4
(
a
), the design value W of channel width is relatively large (W≧1.6 &mgr;m) and the active area
11
is rectangular in shape; for the type shown in
FIG. 4
(
b
), the design value of channel width is scaled down (W<1.6 &mgr;m), with a shorter channel length, so the active area
11
is in so-called “dog bone” shape; for the type shown in
FIG. 4
(
c
), it has a dog-bone shape, with a narrow channel width, but with a longer channel length. As shown in
FIG. 4
(
c
), in an area where the channel width is smaller, the effective value We of channel width is greater than the design value W of channel width. This effect is referred to herein as “effect of stress,” and an error that occurs between W and We due to this “effect of stress” is regarded as &Dgr;W
2
.
Next, an explanation on &Dgr;W
3
is given. If the design value W of channel width is scaled down and the design value L of channel length is scaled down, the geometry of the channel region spreads like a web, as shown in
FIG. 4
(
b
) This is because the corners on the source and drain sides of the channel region are rounded due to light diffraction in photolithography and they influence each other. This effect is referred to herein as “effect of lithography,”

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