Modeling asynchronous behavior from primary inputs and latches

Details Modeling asynchronous behavior from primary inputs and latches Modeling asynchronous behavior from primary inputs and latches

2006-02-23

2008-11-04

Cabrera, Zoila E. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

Reexamination Certificate

active

07447620

ABSTRACT:
Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.

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