Modeling and verification of concurrent systems using...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Software program

Reexamination Certificate

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C703S002000, C711S141000

Reexamination Certificate

active

08005661

ABSTRACT:
A computer implemented method for modeling and verifying concurrent systems which uses Satisfiability-Modulo Theory (SMT)-based Bounded Model Checking (BMC) to detect violations of safety properties such as data races. A particularly distinguishing aspect of our inventive method is that we do not introduce wait-cycles in our symbolic models for the individual threads, which are typically required for considering an interleaved execution of the threads. These wait-cycles are detrimental to the performance of BMC. Instead, we first create independent models for the different threads, and add inter-model constraints lazily, incrementally, and on-the-fly during BMC unrolling to capture the sequential consistency and synchronization semantics. We show that our constraints provide a sound and complete modeling with respect to the considered semantics. One benefit of our lazy modeling method is the reduction in the size of the BMC problem instances, thereby, improving the verification performance in both runtime and memory.

REFERENCES:
Armando et al. “Bounded Model Checking of Software using SMT Solvers instead of SAT solvers”, Jan. 2006, In: SPIN. vol. 3925 of LNCS, pp. 146-162.
Clarke et al. “Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking”, 2003, Procedings of 40th Annual Design Automation Conference, pp. 369-371.

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