Modeling and processing of on-chip interconnect capacitance

Details Modeling and processing of on-chip interconnect capacitance Modeling and processing of on-chip interconnect capacitance

1997-07-03

2000-05-09

Teska, Kevin J.

39550003, 39550009, G06F 1750

Patent

active

060615087

ABSTRACT:
An apparatus and method is presented for capacitance analysis in chip environments for arbitrary geometries. It uses a process which combines 2-dimensional ascertainments where the length is chosen to fit the solution. Also, the required accuracy may be limited to be within an error range. The technique is also applicable for the analysis of three dimensional capacitances, and importantly also for a mixture of two and three dimensional capacitance ascertainments. In an embodiment the process divides the space into a set of subspaces. The capacitance value for the subspaces are determined using the parallel plate capacitance formula.

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