Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-03-22
2001-10-16
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S198000
Reexamination Certificate
active
06304114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mode setting determination signal generation circuit, and in particular, to a memory circuit for generating, during power-up, a mode setting determination signal indicating an initial setting for an operation mode.
2. Description of the Prior Art
Memory devices require an initial setting for their operation mode to be determined during power-up. Thus, the memory device requires a circuit for generating a mode setting determination signal indicating the initial setting for the operation mode.
FIG. 8
shows a conventional mode setting determination signal generation circuit. This circuit is comprised of a NAND circuit
100
, inverters (NOT circuits)
101
,
102
, and transfer circuits (transfer-gates)
103
,
104
.
A POWER-ON signal with negative logic (an output signal from such a circuit as generates a one-shot pulse on power-up. This signal is hereafter referred to as a “POWER-ON signal bar”) is input to one input terminal of the NAND circuit
100
, while output signals from the transfer circuits
103
,
104
are input to the other input terminal thereof.
An output signal from the NAND circuit
100
is input to the inverter
101
, while a mode setting control signal is input to the inverter
102
. A mode setting determination signal serves to select an operation mode of the device. An output terminal of the inverter
101
is connected to a source of the transfer circuit
103
. The mode setting control signal is applied to a first circuit of the transfer circuit
103
, and an output terminal of the inverter
102
is connected to a second circuit thereof. A mode setting signal is applied to a source of the transfer circuit
104
. The output terminal of the inverter
102
is connected to a first circuit of the transfer circuit
104
, and the mode setting control signal is applied to a second circuit thereof.
Drains of the transfer circuits
103
and
104
are both connected to the other input terminal of the NAND circuit
100
.
With this configuration, during power-up, the operation mode is set based on the POWER-ON bar signal (the mode setting determination signal is sent out). First, a mode setting signal applied to the transfer circuit
104
is set to an H level. The applied mode setting signal at the H level is then applied to the other input terminal of the NAND circuit
100
through the transfer circuit
104
. When a POWER-ON signal bar (L level) is applied to one input terminal of the NAND circuit
100
, the output terminal of the NAND circuit
100
is set to the H level. This signal acts as a mode setting determination signal.
FIG. 9
shows another conventional mode setting determination signal generation circuit. This semiconductor storage is comprised of a NOR circuit
110
, inverters
111
,
112
, and transfer circuits
113
,
114
.
The semiconductor storage in
FIG. 9
will have the same overall configuration as the circuit in
FIG. 8
if the NAND circuit
100
in
FIG. 8
is replaced with the NOR circuit
110
. That is, the inverters
111
,
112
correspond to the inverters
101
,
102
, and the transfer circuits
113
,
114
correspond to the transfer circuits
103
,
104
.
With the configuration in
FIG. 9
, during power-up, a POWER-ON signal (H level) sets the operation mode of the circuit. First, a mode setting signal applied to the transfer circuit
104
is set to the H level. In this semiconductor device, the H-level POWER-ON signal is applied to the NOR circuit
110
and to the other input terminal of the NAND circuit
100
through the transfer circuit
104
. The NOR circuit
110
outputs an L-level signal when both input terminals thereof are at the L level. Consequently, when the mode setting signal is at the H level, an L-level mode setting determination signal is output.
In
FIGS. 8 and 9
, once the output of the NAND circuit
100
or NOR circuit
110
has been set to the L level, the corresponding data is latched in the path between the NAND circuit
100
and the inverter
101
or between the NOR circuit
110
and the inverter
111
. As described above, the operation mode is set to the single value during power-up.
In addition, in
FIGS. 8 and 9
, to change the setting for the operation mode after power-up, an externally provided mode setting control signal is shifted from H to L level. Then, the transfer circuit
103
,
113
is turned off and the transfer circuit
104
,
114
is turned on to change the setting for the operation mode.
According to the conventional circuit, however, the setting (mode setting determination signal) for the operation mode is determined simply by the POWER-ON signal during power-up, so that the operation mode can be set only to the H or L level. Although users have recently demanded various initial settings for the operation mode during power power-up, the conventional mode setting determination signal generation circuit cannot deal with such a demand.
BRIEF SUMMARY OF THE INVENTION
Objects of the Invention
It is an object of the present invention to provide a mode setting determination signal generation circuit capable of making a plurality of initial settings for the operation mode during power-up.
SUMMARY OF THE INVENTION
The present invention provides a mode setting determination signal generation circuit for generating a mode setting determination signal based on a power-on signal applied during power-up, comprising:
signal generation means for generating an output signal fixed either to a high or low level, a first logic circuit section for outputting a signal based on a NOR or OR logic between the output signal from the signal generation means and the power-on signal, a second logic circuit section for outputting a signal based on a NAND or AND logic between a power-on signal having a polarity opposite to that of the above power-on signal and the output signal from the signal generation means, a third logic circuit section for outputting a signal based on a NAND or AND logic between a signal at a mode setting determination signal output terminal thereof and the output signal from the second logic circuit section, a transfer gate circuit section for outputting either the output signal from the third logic circuit section or a mode setting signal as an output signal based on a mode setting control signal, and a fourth logic circuit section for outputting a signal based on a NAND or AND logic between the output signal from the transfer gate circuit section and the output signal from the first logic circuit section.
The signal generation means has a first transistor and a second transistor connected in series between a first power supply and a second power supply, and the first and second transistors have different voltage thresholds.
Ions are injected either into the first or second transistor to vary the voltage threshold of this transistor.
REFERENCES:
patent: 5767717 (1998-06-01), Schorn et al.
Cunningham Terry D.
NEC Corporation
Scully Scott Murphy & Presser
Tra Quan
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