Mode setting circuit for a memory device

Details Mode setting circuit for a memory device Mode setting circuit for a memory device

1997-06-19

1999-07-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Fusible link or intentional destruct circuit

365 96, 3652257, H01H 3776

Patent

active

059296917

ABSTRACT:
A mode setting circuit for a semiconductor memory device reduces power consumption and layout area by utilizing a complimentary pair of transistors to sense the state of a fuse. The fuse and complimentary pair of transistors are coupled in series between a power supply and ground. The gates of the transistors are coupled together to receive an input signal. An output signal is generated at a node between the pair of transistors. A latch is coupled to the node to latch the output signal. When the fuse is intact, the circuit generates the output signal responsive to the input signal. When the fuse is blown, the circuit maintains the output signal in a steady state.

REFERENCES:
patent: 4935899 (1990-06-01), Morigami
patent: 4996672 (1991-02-01), Kim
patent: 5345110 (1994-09-01), Renfro et al.
patent: 5361001 (1994-11-01), Stolfa
patent: 5446402 (1995-08-01), Yoshimori
patent: 5539692 (1996-07-01), Kajigaya et al.
patent: 5566107 (1996-10-01), Gilliam

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