Mode optimized D.C. power supply

Details Mode optimized D.C. power supply Mode optimized D.C. power supply

1988-01-19

1989-03-28

Salce, Patrick R.

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

323285, G05F 146

Patent

active

048167401

ABSTRACT:
A D.C. power supply in which the output capacitor used in the CV mode of operation is removed from the output circuit in the CC mode of operation and charged to the voltage between the output terminals so as to prevent transients or switch stressing that could be caused when the output capacitor is reconnected to the output circuit for CV operation. In a preferred embodiment, first and second FET's are connected in series between the input and output terminals of the supply. While the first is used for control during CV operation, the second is in saturation, and while the second is used for control during CC operation, the first is in saturation. The output impedance of the supply is decresed during CV operation by connecting the source electrode of the first FET to the output electrode, and the output impedance of the supply is increased during CC operation by connecting the drain electrode of the second FET to the output electrode.

REFERENCES:
patent: 3303411 (1967-02-01), Gately
patent: 3414803 (1968-12-01), Glasgow et al.

Affiliated with

Also associated with

Rating

Mode optimized D.C. power supply does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mode optimized D.C. power supply, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mode optimized D.C. power supply will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1661788