Mode control of PLL circuit

Details Mode control of PLL circuit Mode control of PLL circuit

2001-01-10

2003-02-25

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S017000, C331S025000, C331S00100A, C331SDIG002, C327S156000, C327S159000, C327S157000

Reexamination Certificate

active

06525612

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a phase-locked loop (PLL) circuit, and more particularly, to mode control of a PLL circuit operated in a high-speed mode and a normal mode.
A PLL circuit operated in a high-speed mode and a normal mode increases the loop gain to perform lockup at a high speed in the high speed mode. Subsequent to the locking, the PLL circuit decreases the loop gain in the normal mode (normal operation mode) to obtain a high carrier noise ratio (C/N) and a low spurious characteristic. The mode switching satisfies the demand for high-speed lockup and the demand for a high C/N and low spurious leak in a lock state.
The PLL circuit has a phase comparator that compares the phase of a reference signal with the phase of an oscillation frequency signal output from a voltage-controlled oscillator (VCO) to generate an up-pulse signal for increasing a frequency of the oscillation frequency signal and a down-pulse signal for decreasing a frequency of the oscillation frequency signal. The pulse width of each signal is based on the comparison result. A charge pump generates current based on the up-pulse and down-pulse signals. A low-pass filter generates a control voltage based on the charge pump output current to control the oscillation frequency signal of the VCO.
In a locked state in which the phases of the reference and oscillation frequency signals are matched, the output of a null current from the charge pump forms a dead zone in the PLL system. To prevent the formation of a dead zone, the phase comparator outputs an up current and a down current. In the locked state, the up and down currents affect the C/N and the spurious leak. Thus, the up and down currents are suppressed in the normal mode.
To shorten the lockup time in the high-speed mode, it is preferred that the charge pump outputs a greater amount of current than in the normal mode or the comparator outputs the up-pulse and down-pulse signals with a greater pulse width than in the normal mode.
The normal mode and the high-speed mode are switched by detecting the lock state from the output signal of the phase comparator. The PLL circuit switches to the normal mode when the difference between the frequencies of the reference signal and the oscillation frequency signal enters a predetermined range and switches to the high-speed mode when the frequency difference goes out of the predetermined range.
However, in the conventional PLL circuit, when the mode is switched from high-speed to normal, the PLL circuit may be released from the lock state causing the phase difference between the reference and oscillation signals to increase. In other words, when a mode signal switches the PLL circuit from a high-speed mode to a normal mode as shown in FIG.
1
(
a
), the frequency lock is released as shown in FIG.
1
(
b
). FIG.
1
(
c
) is an output waveform diagram of the PLL circuit during a frequency lock of a PLL circuit having only the normal mode.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a PLL circuit that maintains a stable locked state when switched from a high-speed mode to a normal mode.
To achieve the above object, the present invention provides a mode control circuit for mode controlling a phase-locked loop (PLL) circuit having a high-speed mode in which a high-speed lockup operation is performed and a normal mode in which a normal PLL operation is performed. The PLL circuit compares the phase of a reference signal and the phase of a comparison signal to generate a first pulse signal and a second pulse signal, and generates based on the first and second pulse signals a frequency signal that is locked at a desired frequency. The mode control circuit receives the first and second pulse signals from the PLL circuit, generates a mode switch signal representing the normal mode when a difference between a phase of the first pulse signal and a phase of the second pulse signal is within a predetermined range, and, after the mode is switched from the high-speed mode to the normal mode, generates the mode switch signal such that the normal mode is maintained.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.


REFERENCES:
patent: 4787097 (1988-11-01), Rizzo
patent: 5546052 (1996-08-01), Austin et al.
patent: 10-145229 (1998-05-01), None

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