Mode control circuit

Details Mode control circuit Mode control circuit

2000-11-22

2002-06-25

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06411243

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a mode control circuit provided inside a semiconductor integrated circuit, which mode control circuit controls actions and functions of the semiconductor integrated circuit based on a control signal from outside.
BACKGROUND OF THE INVENTION
The semiconductor integrated circuit (hereinafter referred to as “IC”) needs to have an increased number of input/output terminals for higher functionality to be achieved, while meeting requirements for smaller sizes, and is necessarily subjected to a limitation on a pitch of the input/output terminals.
A method of performing the original number of functions with a reduced number of input/output terminals is known. The IC is provided with a control terminals for inputting a signal from outside, and an encoder circuit. By changing the voltage level of the signal supplied from outside a greater number of functions or conditions may be controlled without increasing the number of the control terminals.
In particular, recent years have observed serial control systems for a plurality of conventional functions as well as conditions to be controlled with merely one to three control terminals, such as by changing a voltage level of a control signal input into a control terminal, or by time-sequentially changing pulse intervals. The serial control systems are implemented generally by provision of a mode control circuit in the IC.
FIG. 5
is a circuit diagram of a conventional mode control circuit. In particular, this figure shows a mode control circuit of the type in which functions may be selected by changing a voltage level of a control signal input into a single control terminal. This mode control circuit comprises a first comparator
101
which compares the voltage level of a control signal input into a control terminal
100
and a predetermined threshold voltage V
1
and outputs the result of such comparison in the form of a logic level, a second comparator
102
which compares the voltage level of the control signal input into the control terminal
100
and a predetermined threshold voltage V
2
and outputs the result of such comparison in the form of a logic level, and an encoder
110
which receives the comparison results in the form of logical levels from the first comparator
101
and the second comparator
102
input thereto to have only one of the three outputs selected as effective.
The encoder
110
is constituted with an inverter
106
which inverts the logic level output by the first comparator
101
, an inverter
105
which inverts the logic level output by the second comparator
102
, a 2-input NAND gate
107
to which the logic levels output by the first comparator
101
and the second comparator
102
are input. A 2-input NAND gate
108
receives the outputs of the inverter
105
and the inverter
106
. A 2-input NAND gate
109
receives the outputs of the inverter
106
and the logic level output by the second comparator
102
. The NAND gates
107
,
108
, and
109
output signals OUT
1
, OUT
2
, and OUT
3
respectively. In other words, this mode control circuit is adapted to select any of three functions with a single control terminal
100
.
FIG. 6
is a circuit diagram of the first comparator
101
. The second comparator
102
has the same structure. The first comparator
101
comprises a constant current source
120
, a differential pair of PNP transistors TN
11
and TN
12
, a current mirror circuit of NPN transistors TP
11
and TP
12
, a first emitter follower circuit (level shift circuit) made of a resistor R
11
and a PNP transistor TN
13
, a second emitter follower circuit made of a resistor R
12
and a PNP transistor TN
14
, and resistors R
13
and R
14
for dividing a power supply voltage V
cc
to generate the threshold voltage.
In other words, the comparator shown in
FIG. 6
serves as a differential amplifier circuit to output at a node OUT a current proportional to a difference between a voltage level at an input terminal IN (which is the same as the control terminal
100
) and a predetermined voltage (the threshold voltage) across the two terminals of the resistor R
14
. Incidentally, the first emitter follower circuit and the second emitter follower circuit are provided to keep the PNP transistors TN
11
and TN
12
respectively from getting saturated even when a low voltage near a ground potential GND is given to the input terminal IN.
The working of the comparator
101
will be explained here. When the voltage level given to the input terminal IN is lower than a base potential of the PNP transistor TN
14
, that is, when the voltage level of a control signal input into the control terminal
100
is lower than the threshold voltage of the comparator, then the base potential of the PNP transistor TN
11
becomes greater than a base voltage of the PNP transistor TN
12
and therefore the current of the constant current source
120
is nearly all conducted to the PNP transistor TN
11
.
At this time, by a function of the current mirror circuit including the PNP transistors TN
11
and TN
12
, there is a tendency for the PNP transistor TP
12
to draw out a current from the PNP transistor TN
12
so as to conduct the same current as a current conducted via the PNP transistor TN
11
and through the PNP transistor TP
11
. However, because the current of the constant current source
120
is nearly all conducted to the PNP transistor TN
11
as described, the current to be supplied from the PNP transistor TN
12
becomes smaller, with a resultant failure to take out a substantial current from the node OUT, so that a low logic level is output from the comparator.
On the contrary, if the voltage level given to the input terminal IN is higher than the base potential of the PNP transistor TN
14
, that is, when the voltage level of the control signal to be input into the control terminal
100
is higher than the threshold voltage of the comparator, then the base potential of the PNP transistor TN
11
becomes smaller than the base potential of the PNP transistor TN
12
and therefore the current of the constant current source
120
is almost conducted to the PNP transistor TN
12
.
In other words, the PNP transistor TN
11
fails to have a substantial current conducted therethrough, and by a function of the current mirror circuit including the PNP transistors TN
11
and TN
12
, the PNP transistor TP
12
is caused draw out from the PNP transistor TN
12
a faint identical current to a current conducted via the PNP transistor TN
11
and through the PNP transistor TP
11
. Therefore, most of the current supplied from the PNP transistor TN
12
is taken out of the node OUT, with a result that a high logic level is output from the comparator.
Next, working of the mode control circuit will be explained with an assumption that the threshold voltage V
1
of the first comparator
101
to be ⅔ of the power supply voltage V
cc
, and the threshold voltage V
2
of the second comparator
102
to be ⅓ of the power supply voltage V
cc
.
When the voltage level of the control signal is greater than the threshold voltage V
1
of the first comparator
101
(i. e. ⅔ V
cc
), the first comparator
101
and the second comparator
102
both output a high logic level. Accordingly, in the encoder
110
, the NAND gates
108
and
109
output a low logic level and the NAND gate
107
outputs a high logic level. As a consequence, only the signal OUT
1
is selected (i.e. output).
When the voltage level of the control signal is lower than the threshold voltage V
2
of the second comparator
102
(i. e. ⅓ V
cc
), the first comparator
101
and the second comparator
102
both output a low logic level. Accordingly, in the encoder
110
, the NAND gates
107
and
109
output a low logic level and the NAND gate
108
outputs a high logic level. As a consequence, only the signal OUT
2
is output.
Finally, when the voltage level of the control signal intervenes between the threshold voltage V
1
and the threshold voltage V
2
, the first comparator
101
outputs a low logic level and the second comp

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