Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2011-03-22
2011-03-22
Do, Chat C (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S523000, C708S503000
Reexamination Certificate
active
07912887
ABSTRACT:
In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. When the operands to the multiply operation are available, they are inspected. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-forwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream. Upon inspection of the operands, if an unnormal intermediate result or a denormal final result will not occur, the addend may be restored to the multiply-add instruction and the add instruction converted to a NOP.
REFERENCES:
patent: 4727508 (1988-02-01), Williams
patent: 5880984 (1999-03-01), Burchfiel et al.
patent: 5901301 (1999-05-01), Matsuo et al.
patent: 5999960 (1999-12-01), Gerwig et al.
patent: 6714957 (2004-03-01), Lohman
patent: 7225323 (2007-05-01), Siu et al.
patent: 7346643 (2008-03-01), Ho et al.
patent: 2002/0194239 (2002-12-01), Pangal
patent: 2005/0228844 (2005-10-01), Dhong et al.
patent: 2007/0061392 (2007-03-01), Gerwig et al.
patent: 2008/0256161 (2008-10-01), Quinnell et al.
patent: 0901067 (1999-10-01), None
patent: 2185338 (1987-07-01), None
patent: 2003529124 (2003-09-01), None
International Preliminary Report on Patentability—PCT/US07/067649, The International Bureau of WIPO, Geneva Switzerland—Nov. 11, 2008.
International Search Report—PCT/US07/067649, International Search Authority—European Patent Office—Sep. 21, 2007.
Written Opinion—PCT/US07/067649, International Search Authority—European Patent Office—Sep. 21, 2007.
Schwarz, E. et al., “Hardware Implementations of Denormalized Numbers,” Proceedings 16th IEEE Symposium on Computer Arithmetic (Arith 16), IEEE Computer Society, ISBN 0-7695-1894-X, Jun. 2003.
Dockser Kenneth Alan
Lall Pathik Sunil
Do Chat C
Kamarchik Peter M.
Pauley Nicholas J.
Qualcomm Incorporated
Sandifer Matthew
LandOfFree
Mode-based multiply-add recoding for denormal operands does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mode-based multiply-add recoding for denormal operands, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mode-based multiply-add recoding for denormal operands will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2628532