Mode 4 reply decoder

Details Mode 4 reply decoder Mode 4 reply decoder

1989-04-07

1991-03-19

Tarcza, Thomas H.

Cryptography

Particular algorithmic function encoding

Nbs/des algorithm

380 48, 342 45, 36442401, H04K 100, G01S 736

Patent

active

050017519

ABSTRACT:
A reply decoder (30) for declaring mode 4 replies when used with a KIR cryptograph computer (25) is described including timing logic (114), memory (112) for storing mode 4 replies and logic circuitry for analyzing replies stored in the memory (112). The invention further provides logic circuitry for detecting railing (117) i.e., successive replies, for detecting garbled or overlapping replies (123), for providing a floating density value window (114, 120) for summing the replies in nonselected reply positions and for target start/stop determination (215) based on selected criteria. The invention overcomes the problem of declaring excessive mode 4 replies which over burden the subsequent reply processing in a reply processor (50).

REFERENCES:
patent: 3310802 (1967-03-01), Coleman et al.
patent: 4630048 (1986-12-01), Callahan, Jr.
patent: 4630049 (1986-12-01), Callahan, Jr.
patent: 4802216 (1989-01-01), Irwin et al.
patent: 4814769 (1989-03-01), Robin et al.
patent: 4897659 (1990-01-01), Mellon

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