Moat router for integrated circuits

Boots – shoes – and leggings

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Details

364490, 364489, 364488, G06F 1560

Patent

active

048520160

ABSTRACT:
A method of specification of the routing of signal and planar power nets between terminals of a core module and pads in an array of pads surrounding the core module. The method identifies proximity terminals and cyclic constraints and then routes the signal nets and power nets in separate moat rings that are concentric with the core module. The proximity terminals and any pads involved in cyclic constraints are routed in respective proximity and cyclic moat rings, adjacent the core module and pad array, respectively. Finally, the resulting moat signal nets are promoted within the signal to the next most outwardly adjacent, unoccupied concentric tracks, and then sections of the proximity, signal, power, and cyclic rings are collapsed to the next most radially inward, unoccupied concentric tracks. In a further step, the method of the present invention can route each of the possible orientations of the core module with respect to the array of pads, thereby determining the minimum possible chip area for the desired integrated circuit.

REFERENCES:
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4615011 (1986-09-01), Linsker
"An Over-Cell Gate Array Channel Router", H. E. Krohn, IEEE 20th Design Automation Conference, 1983, pp. 665-670.
"A New Two-Dimensional Routing Algorithm", Chi-Ping-Hsu, IEEE 19th Design Automation Conference, 1982, pp. 46-50.
"A New Routing Region Definition and Ordering Scheme Using L-Shaped Channels", Dai et al., IEEE Proceeding of ISCA 1985, pp. 29-30.
"A Routing Program Applicable to Various Chip Structure of Gate Arrays", Terai et al., Ronbunshi, vol. 25, No. 3, May 1984, pp. 357-364.

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