MNOS memory transistor having a redeposited silicon nitride gate

Details MNOS memory transistor having a redeposited silicon nitride gate MNOS memory transistor having a redeposited silicon nitride gate

1976-07-22

1978-06-20

James, Andrew J.

357 54, 357 6, 357 41, 357 56, H01L 2978, H01L 2934, H01L 2702

Patent

active

040965090

ABSTRACT:
A processing technique utilizing two separate silicon nitride depositions (one to form the memory regions and the second to form the nonmemory regions) is employed to provide a radiation hard drain source protected memory transistor. The amount of silicon dioxide used in the nonmemory regions is also minimized. A typical device comprises a mesa etched from a silicon-on-sapphire (SOS) wafer into which P+ source and drain regions are implanted. A 100 A layer of silicon dioxide and a second 1000 A layer of nonmemory silicon nitride covers the mesa and the two layers are etched to define a substrate gate window. The gate window is covered by a 25 A layer of tunneling oxide A final 500 A layer of memory silicon nitride covers the mesa structure. Contact windows are etched to accommodate source, drain and gate interconnect electrodes.

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A Double-Diffused MNOS Transistor as a New Non-Volatile Memory; by Endo IEE Meeting; No. 73 CHO781-5ED 1973.
Improvement of the Gate-Region Integrity in FET Devices; by Abbas et al., IBM Technical Disclosure Bulletin, vol. 14, No. 11, Apr. 1972 pp. 3348-3350.

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