MNOS Memory device

Details MNOS Memory device MNOS Memory device

1976-06-21

1977-12-13

Miller, Jr., Stanley D.

357 54, H01L 2978

Patent

active

040632679

ABSTRACT:
A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect. The IGFET includes an oxide layer having a portion of minimum thickness in the region thereof overlying an interstitial portion of a semiconductive substrate having a pair of spaced semiconductive diffusion regions, a portion of intermediate thickness partially overlying at least one of the pair of diffusion regions and the interstitial substrate portion, and a remaining portion of maximum thickness. The oxide layer portion of minimum thickness has a width greater than the width of an overlying electrically conductive gate electrode; the oxide layer portion of intermediate thickness has a width less than the width of the overlying electrode.

REFERENCES:
patent: 3846768 (1974-11-01), Krick
P. J. Krick, "The Implanted Stepped-Oxide MNOSFET," IEEE Transactions on Electron Devices, Feb. 1975, pp. 62-63.
Electronics, Apr. 1, 1976, p. 89.

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