MNOS Memory cell

Details MNOS Memory cell MNOS Memory cell

1980-04-30

1982-05-18

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365184, 357 23, G11C 1140

Patent

active

043308503

ABSTRACT:
The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate electrode is split into two electrodes, which can be operated in different ways and which are superimposed on upon another. These gate electrodes are connected via self-aligned, overlapped contacts. This arrangement resolves "short channel erasure", even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

REFERENCES:
patent: 3836992 (1974-09-01), Abbas et al.
patent: 4128670 (1978-12-01), Gaensslen
patent: 4225945 (1980-09-01), Kuo
patent: 4227202 (1980-10-01), Tasch et al.
Das Gupta et al. "Dual--Gate FAMOS Memory Cell", IBM Tech. Disc. Bul., vol. 17, No. 8, 1/75, pp. 2266.
Hagiwara et al., "A 16 Bit Electrically Erasable PROM Using N-Channel Si-Gate MNOS Technology," IEEE Jour. of S-S Circuits, vol. SC-15, No. 3, 6/80, pp. 346-353.

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