Mixer structure and method for using same

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals

Reexamination Certificate

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Details

C327S355000, C327S356000, C327S113000, C455S333000

Reexamination Certificate

active

06512408

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mixer, and more particularly, to a multi-phase mixer and methods for using same.
2. Background of the Related Art
Presently, a radio frequency (RF) communications system has a variety of applications including PCS communication and IMT systems. As such, a CMOS chip integration of the system has been pursued to reduce the cost, size and power consumption.
Generally, the RF communication system is composed of RF front-end block and base-band digital signal processing (DSP) block. Currently, the base-band DSP block can be implemented with low cost and low power CMOS technology. However, the RF front-end cannot be implemented by CMOS technology due to fundamental limits in speed and noise characteristics, which are below the speed and noise specification of popular RF communication systems.
For example, the PCS hand-phone system operate at a frequency over 2.0 GHz, but current CMOS technology can support reliably operation only up to a frequency of 1.0 GHz in terms of speed and noise. Hence, the RF front-end block is implemented using bipolar or bi-CMOS technology that has better speed and noise characteristics than CMOS technology, but is more expensive and consumes more power.
One of the main causes for the 1 GHz limitation is the structure of the VCO and the mixer.
FIG. 1
is a circuit diagram of the VCO-mixer according to a background art. As shown in
FIG. 1
, the VCO
10
includes four differential delay cells
12
,
14
,
16
and
18
and has a structure similar to a ring oscillator. The four delay cells
12
-
18
are serially connected and generate a clock signal LO+ and an inverted clock signal LO−, each having a frequency of f
0
. A control circuit for the VCO
10
that generates a frequency control signal includes a phase frequency detector
4
, a charge pump
6
and a loop filter
8
that outputs the frequency control signal to each of the delay cells
12
-
18
. The phase frequency detector
4
receives a reference clock signal f
ref
and a VCO clock signal f
vco
from a reference clock divider circuit
2
and a VCO clock divider circuit
3
, respectively. The frequency f
0
of the clock signals LO+ and LO− is represented by M/K (f
ref
)=f
0
. Thus, the frequency f
0
is based on the reference clock signal f
ref
and the divider circuits
2
and
3
.
The mixer
20
, such as Gilbert—Multiplier, multiplies the input signals, such as radio frequency (RF) signals RF+ and RF−, with the clock signals LO+ and LO−. The mixer
20
includes two load resistors R
1
and R
2
coupled to a source voltage V
DD
, eight NMOS transistors
21
-
28
, and a current source I
S1
. The gates of the NMOS transistors
21
and
22
are coupled to receive the clock signal LO+, and the gates of the NMOS transistors
23
and
24
are coupled to receive the inverted clock signal LO−. The gates of the NMOS transistors
25
and
26
receive a common bias voltage V
Bias
. The gates of the NMOS transistors
27
and
28
receive the RF signals RF+ and RF−, respectively. Therefore, the clock signals LO+ and LO− are multiplied with the RF signals RF+ and RF− only when the transistors
25
and
27
or the transistors
26
and
28
are turned on together. The output signals OUT+ and OUT− of the mixer
20
has a frequency lower than its original frequency by the frequency f
0
of the clock signals LO+, LO−.
As discussed above, a wide frequency range and a low phase noise are desirable for various applications. However, the VCO-mixer structure
10
and
20
can only support up to a frequency 1 GHz with reliable phase noise and frequency range. The performance of the VCO-mixer structure
10
and
20
becomes worse in terms of phase noise and frequency range and is unacceptable as the frequency of the clock signals LO+ and LO− from the VCO increases. Hence, the VCO
10
and the mixer
20
cannot be readily implemented when the frequency f
0
of the clock signals LO+ and LO− is over 1 GHz.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
A further object of the present invention is to provide a VCO-mixer and method for using same on a single substrate.
Another object of the present invention is to increase the frequency range of a apparatus mixer and method.
Still another object of the present invention is to provide a mixer and method for using same having reduced noise.
Another object of the present invention is to increase a performance of the mixer structure.
A further object of the present invention is to provide a single/double balanced mixer and method having a symmetric switch structure.
A further object of the present invention is to fabricate a RF communications receiver on a single substrate.
A further object of the present invention is to provide a RF communications transceiver and method including a multi-phase mixer on a single substrate.
To achieve the advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a circuit that includes a mixer that receives a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than a reference frequency, wherein the mixer mixes the plurality of first clock signals to generate a plurality of local oscillator signals therein having a higher second frequency, and wherein the mixer multiplies the plurality of local oscillator signals with input signals to provide output signals at output terminals.
To further achieve the advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a method for modulating input signals that includes generating a plurality of first clock signals having different phases, each first clock signal having a first frequency that is less than a reference frequency of an input signal, combining the plurality of first clock signals to generate a plurality of local oscillator signals having a second frequency higher than the first frequency and mixing the plurality of local oscillator signals with the input signal to provide an output signal.
To further achieve the advantages and in accordance with the purpose of the present invention, as embodied and broadly described, there is provided a receiver that includes an antenna that receives input signals being analog RF signals, a low noise amplifier coupled to the antenna, a clock generator that receives a reference signal having a reference frequency that generates a plurality of first clock signals having N different phases, N being an integer greater than two, each first clock signal having a first frequency substantially equal to double the reference frequency divided by N, a mixer coupled to the clock generator and the low noise amplifier that receives the plurality of first clock signals to generate at least one local oscillator signal therein having approximately the second frequency, wherein the mixer multiplies the at least one local oscillator signal with input signals to provide output signals at output terminals, a channel selection filter that removes an out-of-band signal from the demodulated baseband signal and an analog-to-digital converter that converts the demodulated baseband signal to a digital data stream.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particu

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