Mixer circuit having component for frequency conversion

Details Mixer circuit having component for frequency conversion Mixer circuit having component for frequency conversion

2000-04-11

2004-11-30

Tran, Pablo N. (Department: 2685)

Telecommunications

Receiver or analog modulated signal frequency converter

Frequency modifying or conversion

C455S319000, C455S327000, C455S333000, C327S359000, C327S361000

Reexamination Certificate

active

06826393

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to mixer circuits, and more particularly to a high gain mixer circuit.
2. Description of the Background Art
A conventional Gilbert cell type mixer circuit
1000
will be described with reference to FIG.
12
. Mixer circuit
1000
includes a constant current source
1007
which supplies a constant current 2×IEE, and transistors
1003
to
1006
. Here, V
1
, V
2
, i
1
, and i
2
denote a first input voltage, a second input voltage, a first output current, and a second output current, respectively.
Transistors
1003
,
1004
have their emitter terminals connected commonly to each other, and transistors
1005
,
1006
also have their emitter terminals connected commonly to each other. Transistors
1003
,
1005
have their collector terminals connected commonly to each other, and transistors
1004
,
1006
also have their collector terminals connected commonly to each other.
The collector terminal of transistor
1001
is connected to the common emitter terminal of transistors
1003
,
1004
, and the collector terminal of transistor
1002
is connected to the common emitter terminal of transistors
1005
,
1006
.
Transistors
1001
,
1002
have their emitter terminals connected to constant current source
1007
.
Mutually complementary voltages V
1
+, V
1
− are input to the bases of transistors
1001
,
1002
. Voltage V
2
+ is input to the bases of transistors
1003
,
1006
, and voltage V
2
− is input to the bases of transistors
1004
,
1005
. Voltages V
2
+, V
2
− are mutually complementary.
First output current il is output from the collector terminals of transistors
1003
,
1005
, and second output current i
2
is output from the collector terminals of transistors
1004
,
1006
.
The operation will be described in the following. First input voltage V
1
and second input voltage V
2
are signals having mutually different frequencies f
1
, f
2
. The input signals having frequency f
1
are converted to the collector currents of transistors
1001
,
1002
and amplified by an emitter coupled pair circuit which is formed of transistors
1001
,
1002
.
The collector currents of transistors
1001
,
1002
serve as a tail current for an emitter coupled pair circuit which is formed of transistors
1003
,
1004
and for an emitter coupled pair circuit which is formed of transistors
1005
,
1006
.
The input signals having frequency f
2
are amplified respectively by the emitter coupled pair circuit which is formed of transistors
1003
,
1004
and by the emitter coupled pair circuit which is formed of transistors
1005
,
1006
.
This relation is represented by the following equations. Here, VT is a thermal voltage, V
1
=(V
1
+)−(V
1
−), and V
2
=(V
2
+)−(V
2
−). The collector currents of transistors
1001
,
1002
are ic
1
, ic
2
which are represented by equations (1), (2).
ic
1
=2
IEE
/{1+exp(−
V
1
/
VT
)}  (1)
ic
2
=2
IEE
/{1+exp(
V
1
/
VT
)}  (2)
When the collector currents of transistors
1003
,
1004
,
1005
, and
1006
are ic
3
, ic
4
, ic
5
, and ic
6
, then ic
3
to ic
6
are represented by equations (3) to (6).
ic
3
=
ic
1
/{1+exp(−
V
2
/
VT
)}  (3)
ic
4
=
ic
1
/{1+exp(
V
2
/
VT
)}  (4)
ic
5
=
ic
2
/{1+exp(
V
2
/
VT
)}  (5)
ic
6
=
ic
2
/{1+exp(−
V
2
/
VT
)}  (6)
From equations (1) to (6), ic
3
, ic
4
, ic
5
, ic
6
, V
1
, and V
2
satisfy equations (7) to (10).
ic
3
=2
IEE
/[{1+exp(−
V
1
/
VT
)}·{1+exp(−
V
2
/
VT
)}]  (7)
ic
4
=2
IEE
/[{1+exp(−
V
1
/
VT
)}·{1+exp(
V
2
/
VT
)}]  (8)
ic
5
=2
IEE
/[{1+exp(
V
1
/
VT
)}·{1+exp(
V
2
/
VT
)}]  (9)
ic
6
=2
IEE
/[{1+exp(
V
1
/
VT
)}·{1+exp(−
V
2
/
VT
)}]  (10)
From the forgoing, the differential output current is represented by the following expression.
 
i
1
−
i
2
=
ic
3
+
ic
5
−(
ic
6
+
ic
4
)=2
IEE
·{tan
h
(
V
1
/
2
VT
)}·{tan
h
(
V
2
/
2
VT
)}  (11)
Here, tanh can be expanded in series as in equation (12). If x is sufficiently smaller than 1, equation (13) is formed.
tan
h
(
x
)=
x−x·x·x
/3  (12)
tan
h
(
x
)≈
x
  (13)
The relation between input voltages V
1
, V
2
and differential output currents i
1
, i
2
is represented by equation (14).
i
1
−
i
2
≈2
IEE
·(
V
1
/
2
VT
)·(
V
2
/
2
VT
)  (14)
In short, mixer circuit
1000
is a circuit for multiplying input voltages V
1
, V
2
. That is, input voltages V
1
, V
2
are signals having mutually different frequencies f
1
, f
2
. Therefore, by multiplying the two signals, mixer circuit
1000
performs the mixer operation of outputting a signal having a frequency component of the sum (|f
1
+f
2
|) or the difference (|f
1
−f
2
|) of the frequencies of the two signals.
In the following, each of mixer circuits
1100
,
1300
disclosed in Japanese Patent Laying-Open No. 10-322135 will be described.
A low voltage type mixer circuit
1100
will be first described with reference to FIG.
13
. Mixer circuit
1100
includes constant current sources
1015
,
1016
which supply a constant current IEE, transistors
1011
to
1014
, and a 180° phase shifter
1017
. Here, in
1
, in
2
, Out+, and Out− are a first input signal, a second input signal, a positive output current, and a negative output current, respectively.
Transistors
1011
,
1012
have their emitter terminals connected commonly to each other, and transistors
1013
,
1014
also have their emitter terminals connected to each other. Transistors
1011
,
1013
have their collector terminals connected commonly to each other, and transistors
1012
,
1014
also have their collector terminals connected commonly to each other.
The common emitter terminal of transistors
1011
,
1012
is connected to constant current source
1015
via a node A. The common emitter terminal of transistors
1013
,
1014
is connected to constant current source
1016
via a node B. First input signal in
1
is input to node A. Between node A and node B, the 180° phase shifter is provided. The common emitter terminal of transistors
1011
,
1012
and the common emitter terminal of transistors
1013
,
1014
are connected via 180° phase shifter
1017
.
Signal in
2
+ is input to the bases of transistors
1011
,
1013
, and signal in
2
− is input to the bases of transistors
1012
,
1013
. Positive output current Out+ is output from the common collector terminal of transistors
1011
,
1013
, and negative output current Out− is output from the common collector terminal of transistors
1012
,
1014
.
180° phase shifter
1017
outputs to node B a signal which has its phase inverted by 180° from that of first input signal in
1
at node A. If the current component of first input signal in
1
is iin
1
, current iA is iA=IEE+iin
1
and current iB B is iB=IEE−iin
1
.
The operation will be described in the following. First input signal in
1
and second input signal in
2
are signals having mutually different frequencies f
1
, f
2
. The common emitter terminal of transistors
1011
,
1012
and the common emitter terminal of transistors
1013
,
1014
are connected commonly via 180° phase shifter
1017
. Therefore, differential input currents are obtained at the common emitter terminal of the coupled pair which is formed of transistors
1011
,
1012
and at the common emitter terminal of the coupled pair which is formed of transistors
1013
,
1014
.
Since the complementary input signals are obtained at nodes A, B, the current amplitude is twic

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