Telecommunications – Receiver or analog modulated signal frequency converter – Frequency modifying or conversion
Reexamination Certificate
1998-09-17
2001-04-17
Maung, Nay (Department: 2681)
Telecommunications
Receiver or analog modulated signal frequency converter
Frequency modifying or conversion
C455S118000, C455S323000, C327S113000, C327S356000
Reexamination Certificate
active
06219536
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an analog mixer circuit for down-converting an RF (Radio Frequency) signal into an IF (Intermediate Frequency) signal or up-converting an IF signal into an RF signal, by mixing an LO (LOcal frequency) signal.
FIG. 4
is a circuit diagram illustrating a conventional mixer circuit. A mixer IC
73
comprises a transistor
50
, whereof a collector is coupled to an output terminal
55
, a base is coupled to an input terminal
54
and an emitter is coupled to a ground terminal
57
. The collector is connected to a power supply terminal
56
through a resistor
51
. The base of the transistor
50
is connected to the ground terminal
57
through a resistor
53
and connected to the collector through a resistor
52
.
Between the power supply terminal
56
and the ground terminal
57
, a power supply voltage Vcc is supplied. The input terminal
54
is connected to an end of a capacitor
61
. To the other end of the capacitor
61
, an LO signal, which is input to an LO terminal
68
, and an IF signal, which is input to an IF terminal
69
, are connected through a BEF (Band Elimination Filter)
71
and a BEF
72
, respectively. The output terminal
55
is connected to an RF terminal
70
through a capacitor
62
and a HPF (High Pass Filter)
67
.
The BEF
71
comprises two capacitors
58
and
59
serially connected between the LO terminal
68
and the capacitor
61
, and an inductance
63
grounding a connecting point of the two capacitors
58
and
59
. The BEF
72
comprises two inductances
64
and
65
serially connected between the IF terminal
69
and the capacitor
61
, and a capacitor
60
grounding a connecting point of the two inductances
64
and
65
.
The BEFs
71
and
72
are provided for isolating the LO signal and the IF signal to be supplied to the capacitor
61
from each other, and the circuit constants thereof are so determined that the BEF
71
shows sufficiently high impedance to the IF signal and the BEF
72
shows sufficiently high impedance to the LO signal. Therefore, the LO signal and the IF signal are added to the input terminal
54
of the mixer IC
73
without interfering with each other. The added signal is amplified nonlinearly by the transistor
50
and output to the output terminal
55
, wherefrom a high-frequency component is extracted by the HPF
67
to be output through the RF terminal
70
.
However, for isolating the LO and the IF signal from each other, the conventional mixer circuit of
FIG. 1
necessitates the BEFs
71
and
72
, which are inconvenient to be configured on an IC (Integrated Circuit) chip, taking large circuit spaces.
For dealing with this problem, there is disclosed a prior art in a Japanese patent application laid open as a Provisional Publication No. 154019/'96.
FIG. 5
is a circuit diagram illustrating a mixer circuit of this prior art.
In the mixer circuit of
FIG. 5
, a mixer IC
98
comprises transistors
74
,
75
and
76
, bias circuits
80
and
81
, resistors
77
and
78
and a capacitor
84
.
The base of the transistor
74
connected to an LO input terminal
87
of the mixer IC
98
is biased by the bias circuit
80
connected between a power supply terminal
89
and a ground terminal
90
, and the base of the transistor
75
connected to an IF input terminal
88
of the mixer IC
98
is biased by the bias circuit
81
also connected between the power supply terminal
89
and the ground terminal
90
.
The emitters of the transistors
74
and
75
are connected to the ground terminal
90
. The collectors of the transistors
74
and
75
are coupled and connected to the power supply terminal
89
through the resistor
77
.
The base of the transistor
76
is connected to the collectors of the transistors
74
and
75
. The resistor
78
and the capacitor
84
are connected in parallel between the emitter of the transistor
76
and the ground terminal
90
. The collector of the transistor
76
is connected to an output terminal
91
of the mixer IC
98
.
An LO signal supplied to an LO terminal
95
is input to the LO input terminal
87
through a capacitor
82
, and an IF signal supplied to an IF terminal
96
is input to the IF input terminal
88
through a capacitor
83
. A power supply voltage Vcc is supplied between the power supply terminal
89
and the ground terminal
90
. Tile output terminal
91
is connected to an end of a HPF
94
. The other end of the HPF
94
is connected to an RF terminal
97
through a capacitor
86
and to the power supply terminal
89
through a resistor
79
.
In the mixer circuit of
FIG. 5
, the LO signal input to the LO input terminal
87
of the mixer IC
98
and the IF signal input to the IF input terminal
88
are isolated from each other by the transistors
74
and
75
, and mixed signal thereof obtained at coupled collectors of the transistors
74
and
75
is amplified nonlinearly by the transistor
76
. The RF signal is extracted by the HPF
94
to be output through the RF terminal
97
.
Thus, a mixer circuit is realized in the prior art of
FIG. 5
without needing any BEF for isolating input LO and IF signals from each other.
However, the mixer circuit of
FIG. 5
necessitates two input transistors
74
and
75
driven in parallel. Hence, power consumption of the mixer circuit of
FIG. 5
becomes considerably high.
SUMMARY OF THE INVENTION
Therefore, a primary object of the present invention is to provide an analog mixer circuit which does not need any BEF for isolating two input signals, and can operate at the same time with lower power consumption than the prior art of FIG.
5
.
In order to achieve the object, a mixer circuit of the invention comprises:
a first transistor, a collector thereof being connected to a power supply terminal, an emitter thereof connected to a node and a base thereof connected to a first input terminal;
a second transistor, a base thereof being connected to a second input terminal, an emitter thereof connected to a ground terminal and a collector thereof connected to the node;
a first bias circuit for biasing base potential of the first transistor;
a second bias circuit for biasing base potential of the second transistor;
a third transistor, a base thereof being connected to the node and a collector thereof connected to an output terminal;
a first resistor connected between the collector of the third transistor and the power supply terminal, and;
a parallel connection of a second resistor and a capacitor connected between an emitter of the third transistor and the ground terminal.
When the mixer circuit is used as all up-converter, an LO signal is supplied to the first input terminal through a capacitor and an IF signal is supplied to the second input terminal through another capacitor, for obtaining an RF signal through a HPF from the output terminal.
The IF signal supplied to the base of the second transistor is little affected by the potential of the node. The LO signal supplied to the base of the first transistor is a little affected by the potential of the node. However, the amplitude of the IF signal is sufficient to be comparatively low. Therefore, a sufficient isolation of the IF signal and the LO signal from each other is obtained without needing any BEF, enabling to economizing the circuit size.
Further, the isolation of the two input signals is realized with a serial connection of the first and the second transistor. Therefore, the current consumption can be reduced than the mixer circuit of the prior art wherein a parallel connection of two transistors is used for isolating two input signals.
The mixer circuit may comprise:
a first FET (Field Effect Transistor), whereof a drain is connected to a power supply terminal, a source is connected to an mixed signal output terminal and a gate connected to a first input terminal;
a bias circuit for biasing the gate of the first FET;
a second FET, whereof a drain connected to the mixed signal output terminal and a gate connected to a second input terminal;
a parallel connection of a first resistor and a first capacitor connected betw
Maung Nay
NEC Corporation
Persino Raymond
Sughrue Mion Zinn Macpeak & Seas, PLLC
LandOfFree
Mixer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mixer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mixer circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2473406