Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Combining of plural signals
Reexamination Certificate
2000-10-24
2002-05-28
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific input to output function
Combining of plural signals
C327S359000
Reexamination Certificate
active
06396330
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a mixer circuit, and more particularly to a gilbert cell type double-balanced mixer circuit with small distortion.
2. Description of the Related Art
A radio-signal transceiver such as a presently remarkably spreading cellular phone has a radio-frequency signal receiver operating under a super heterodyne system wherein as a received radio-frequency (RF) signal is converted to an intermediate frequency (IF) signal having a smaller frequency, the received signal is amplified up to a desired signal level. A circuit converting a frequency of a radio-frequency signal in a radio-signal transceiver is called a down converter, and a circuit accomplishing a main function of a down converter is a mixer circuit.
A down converter dealing with a frequency in the rage of 800 MHz to 2 GHz, such as a frequency of a radio-signal in a cellular phone, is generally designed to include a double-balanced mixer circuit having a gilbert cell. Herein, a gilbert cell is a circuit including a first circuit comprised of a pair of transistors each having an emitter grounded, and a second circuit comprised of a first pair of transistors each having an emitter grounded and a second pair of transistors each having an emitter grounded such that the transistors of the first pair and the transistors of the second pair are cross-arranged, the first circuit being electrically connected in series to the second circuit.
A gilbert cell referred to in the specification corresponds to the gilbert type multiplication circuit described at page 171 in the book titled “Technique for designing an analog integrated circuit for VLSI” published by Baifukan, authored by Gray and Meyer, and translated by Jyo Nagata.
FIG. 1
is a circuit diagram illustrating an example of a conventional double-balanced mixer circuit including a gilbert cell.
The illustrated mixer circuit is comprised of a first pair of input terminals
5
A and
5
B through which RF signals are input, a second pair of input terminals
6
A and
6
B through which local signals are input, a first transistor
2
E, a second transistor
2
F, a third transistor
2
A, a fourth transistor
2
D, a fifth transistor
2
B, a sixth transistor
2
C, a resistor
3
A, a first output terminal
7
A through which an IF signal is output, a second output terminal
7
B through which an IF signal is output, a power supply terminal
8
electrically connected to a power supply (not illustrated), a first load
14
A, and a second load
14
B.
In the mixer circuit illustrated in
FIG. 1
, the first to sixth transistors
2
E,
2
F,
2
A,
2
D,
2
B and
2
C and the resistor
3
A, enclosed with a broken line, defines a gilbert cell
1
.
The input terminal
5
A is electrically connected to a base of the first transistor
2
E, and the input terminal
5
B is electrically connected to a base of the second transistor
2
F.
Emitters of the first and second transistors
2
E and
2
F are electrically connected to each other, and are electrically connected further to a ground
12
through the resistor
3
A.
The input terminal
6
A is electrically connected to bases of both the third and fourth transistors
2
A and
2
D, and the input terminal
6
B is electrically connected to bases of both the fifth and sixth transistors
2
B and
2
C.
Emitters of the third and fifth transistors
2
A and
2
B are electrically connected to each other, and are electrically connected further to a collector of the first transistor
2
E. Similarly, emitters of the sixth and fourth transistors
2
C and
2
D are electrically connected to each other, and are electrically connected further to a collector of the second transistor
2
F.
Collectors of the third and sixth transistors
2
A and
2
C are electrically connected to each other, and are electrically connected further to the first output terminal
7
A. The collectors of the third and sixth transistors
2
A and
2
C are electrically connected to the power supply terminal
8
through the first load
14
A.
Collectors of the fifth and fourth transistors
2
B and
2
D are electrically connected to each other, and are electrically connected further to the second output terminal
7
B. The collectors of the fifth and fourth transistor
2
B and
2
D are electrically connected to the power supply terminal
8
through the second load
14
B.
The mixer circuit illustrated in
FIG. 1
constitutes a double-balanced mixer circuit wherein RF and local signals are input in a balanced input style. Herein, a balanced input style means a style where there are two input terminals, and a signal is input across the two input terminals.
In operation, the mixer circuit illustrated in
FIG. 1
outputs results of multiplication of signals input through the RF input terminals
5
A and
5
B and the local input terminals
6
A and
6
B, through the first and second IF output terminals
7
A and
7
B. Hence, a signal having a frequency equal to a sum of frequencies of the RF and local signals and a signal having a frequency equal to a difference between frequencies of the RF and local signals are output through the first and second IF output terminals
7
A and
7
B.
A down converter selects the signal having a frequency equal to a difference between frequencies of the RF and local signals, through a filter, and transmits the thus selected signal to a subsequent IF amplifier.
In the conventional mixer circuit illustrated in
FIG. 1
, since a collector current exponentially changes relative to a base voltage in the first and second transistors
2
E and
2
F to which RF signals are input through the input terminals
5
A and
5
B, distortion is likely to be generated in the first and second transistors
2
E and
2
F.
In order to eliminate such distortion, Japanese Unexamined Patent Publication No. 4-17405 has suggested such a mixer circuit as illustrated in FIG.
2
.
The mixer circuit illustrated in
FIG. 2
additionally includes a second resistor
3
B and a third resistor
3
C in comparison with the mixer circuit illustrated in FIG.
1
.
The second resistor
3
B is electrically connected at one end to an emitter of the first transistor
2
E, and at the other end to both the first resistor
3
A and the third resistor
3
C. Similarly, the third resistor
3
C is electrically connected at one end to an emitter of the second transistor
2
F, and at the other end to both the first resistor
3
A and the second resistor
3
B.
The mixer circuit illustrated in
FIG. 2
can linearize characteristics of both a collector voltage and a base voltage to thereby reduce distortion.
Japanese Unexamined Patent Publication No. 11-27170 has suggested another mixer circuit in order to eliminate the above-mentioned distortion.
FIG. 3
is a circuit diagram of the mixer circuit suggested in the Publication.
The mixer circuit illustrated in
FIG. 3
has the same structure as that of the mixer circuit illustrated in
FIG. 1
except including a first resistor
3
a,
a second resistor
3
b
and a third resistor
3
c
in place of the resistor
3
A.
The first resistor
3
a
is electrically connected at one end to an emitter of the first transistor
2
E, and at the other end to the ground
12
. The second resistor
3
b
is electrically connected at one end to an emitter of the second transistor
2
F, and at the other end to the ground
12
. The third resistor
3
c
is electrically connected to emitters of both the first and second transistors
2
E and
2
F.
However, the above-mentioned mixer circuits illustrated in
FIGS. 1
to
3
are accompanied with a problem that since the resistors electrically connected to emitters of the transistors act as a feedback resistor, resulting in a loss in a conversion gain.
Representing a resistance of the feed-back resistor as “R”, if a collector current varies by &Dgr;Ic, an emitter voltage varies by R×&Dgr;Ic. The variation of an emitter voltage by R×&Dgr;Ic cancels a voltage Vbe between a base and an emitter. That is, since an input voltage Vin is represented as (Vbe+R×&Dgr;Ic), the voltage Vbe is repre
NEC Corporation
Nguyen Long
Tran Toan
Whitham Curtis & Christofferson, P.C.
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