Coded data generation or conversion – Sample and hold
Reexamination Certificate
2003-02-25
2004-03-02
Tokar, Michael (Department: 2858)
Coded data generation or conversion
Sample and hold
C341S120000, C324S076190, C324S076230, C324S076240
Reexamination Certificate
active
06700516
ABSTRACT:
BACKGROUND
The present invention concerns sampling methods used within electronic instruments such as oscilloscopes and pertains particularly to mixer-based timebase for signal sampling.
Eye diagram analysis is an important tool for studying the behavior of high-speed digital electrical and optical communications signals. An eye diagram is a way of displaying on an oscilloscope the waveform shapes of all logic one-zero combinations. It is generated by applying a data waveform to the vertical channel of an oscilloscope while triggering from a synchronous clock signal.
Currently, at data rates below about 3 gigabits per second (Gb/s), real-time sampling oscilloscopes are commonly used. A real-time sampling oscilloscope employs a very high speed analog-to-digital (A/D) converter to capture a waveform record consisting of a complete sequence of successive data bits. The advantage of real-time sampling is that it allows visualization of the exact characteristics of a data pattern that precedes a waveform error such as slow risetime or excessive overshoot.
The A/D converter in a real time sampling oscilloscope must sample the waveform much faster than the data rate. Shannon's sampling theorem states that to unambiguously reconstruct a sine wave the sample rate must be at least twice the signal frequency. In reality, since digital data signals are not simple sine waves, an even higher sampling rate must be used. Most commercial real-time sampling oscilloscopes employ sampling rates of 4-10 times the data rate.
Currently, the fastest commercial real-time sampling oscilloscopes on the market today are limited to about 6 gigahertz (GHz) bandwidth and 20 gigasamples (GSamp/s) sample rates. This bandwidth is useful only for data rates up to about 2.5 gigabits (Gb/s). For higher data rates, equivalent-time sampling technology is used.
One type of architecture used in an equivalent-time sampling system utilizes sequential timebase circuitry that detects a synchronous trigger event (such as a rising or falling edge in the applied trigger signal) and generates a precision programmable delay between the trigger event and the sample strobe. The precision delay generator is typically divided into a course and fine delay generator. Samples are taken at varying times determined by the timebase delay. Each trigger event causes the oscilloscope to take a single sample of the data waveform and display the sample as a single point on the screen. Each subsequent sample point (following a new trigger event) is increasingly delayed relative to the time of the trigger. After numerous trigger events, the oscilloscope fills the display with a sampled representation of the data pattern.
Another type of architecture used in an equivalent-time sampling system utilizes pseudo-random sampling. In pseudo-random sampling systems, the timing of the samples is typically not related to the repetitive signal input. The position of each sample on the time axis of the oscilloscope display is obtained by measuring the timing of each sample relative to an applied reference signal. See, for example U.S. Pat. No. 4,884,020 where a sinusoidal reference is sampled in quadrature to precisely determine the timing of the samples. For additional background information on random electrical sampling, see, for example, U.S. Pat. No. 5,315,627, U.S. Pat. No. 4,928,251, U.S. Pat. No. 4,719,416, U.S. Pat. No. 4,578,667 and U.S. Pat. No. 4,495,586.
The components used in timebase circuitry in existing sampling systems are quite complex and expensive. It is desirable, therefore, to more economically implement timebase circuitry.
SUMMARY OF THE INVENTION
In accordance with the preferred embodiment of the present invention, signal sampling is performed. A sampler takes samples of a sampled signal. A first analog-to-digital (A/D) converter receives the samples from the sampler. A clock reference is synchronous with the sampled signal. A phase comparator produces a difference value that indicates a phase difference between the clock reference and an oscillating signal. A second A/D converter receives the difference value. The oscillating signal is used in controlling when the sampler takes samples of the sampled signal.
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Agilent Technologie,s Inc.
Nguyen Khai
Tokar Michael
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