Coded data generation or conversion – Analog to or from digital conversion – Differential encoder and/or decoder
Reexamination Certificate
2001-04-16
2003-02-04
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Differential encoder and/or decoder
C341S118000, C341S120000, C341S163000
Reexamination Certificate
active
06515604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of sigma-delta mixed signal processors, and more specifically, to a mixed signal processing unit with non-linear feed-forward paths between sigma-delta modulator stages to improve total harmonic distortion (THD) and noise characteristics of the processor.
2. Description of Related Art
A basic mixed signal processor using a sigma-delta modulator includes a sigma-delta loop used to drive a pair of output transistors. The sigma-delta loop includes at least one integrator configured to receive an input signal, a quantizer coupled in series with the output of the modulator and a feedback loop including a digital-to analog converter coupled between the output of the quantizer and the input of the integrator. The feedback signal forces the low frequency components of the output signal of the quantizer to track the low frequency components of the input signal at the integrator input. Any difference between the quantized output and the input signal is accumulated in the integrator and is corrected.
The quantizer is essentially a analog- to -digital converter with a sampling frequency fs. The “order” of a sigma-delta modulator depends on the number of integrators provided in the loop. First, second and third order sigma-delta modulators include one, two and three integrators coupled in series in the loop respectively. For is more information, see for example H. Ballan and M. Declercq, 12 V I-A Class-D Amplifier in 5V CMOS Technology, pp. 559-562 (IEEE 1995 Custom Integrated Circuit Conference), the entirety of which is incorporated herein by reference.
An improvement to standard sigma-delta technology is described in commonly assigned U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXEDSIGNAL PROCESSING the entire specification of which is incorporated herein by reference. In that patent an oversampled, noise-shaping modulator is described which employs continuous-time feedback from the output of its output stage rather than the digital (i.e.state) feedback from before the power switching stage. The continuous-time feedback is provided in such a way as to reduce the aliasing effects on the feedback path introduced by the switching stage which might otherwise interfere with the baseband to an unacceptable degree. That is, the modulator of the abovedescribed patent combines the use of continuous-time feedback to compensate for low frequency distortion and to attenuate the aliasing effects of high frequency distortion introduced via the feedback path. The improved sigma-delta processor therefore provides an efficient, low noise alternative to the traditional sigma-delta processor for a wide variety of applications.
All mixed signal processors using sigma-delta modulators are plagued with a problem of noise with certain high-end applications, such as audio amplifiers. One source of noise, called quantization error, in the signal band is caused by the signal sampling performed by the quantizer. With relatively low input signals, the quantized noise is essentially shaped out by the feedback path while the processor maintains a linear transfer function for the input signals. In fact, the larger the order of the processor, the better the noise shaping characteristics. Second and third order modulators are therefore generally more preferable than single order modulators. For a thorough discussion of sigmadelta modulation noise, see Candy and Temes,
Oversampling Delta-Sigma Data Converters, pp.
1-25 (IEEE Press, 1992), the entirety of which is incorporated herein by reference.
Distortion is another problem associated with mixed signal processors using sigma-delta modulators. For example, in audio applications, power MOS transistors drive relatively low impedances and must therefore have output impedances smaller than one ohm for good overall efficiency.
As a result, the switching characteristics of such transistors are relatively slow, varying from an ideal switching characteristic in an asymmetric way, and thereby generating distortion. Because standard sigma-delta modulators employ digital or state feedback, the asymmetric edges of the power transistor output are not seen by the integrator stages. Consequently, standard sigma-delta modulators are not able to correct for the distortion introduced by the power MOS transistors because of the use of state feedback.
The aforementioned noise and distortion problems are exasperated when the input signal provided to the processor increases. Sigma-delta modulators are non-linear loops and input signal dependant for large inputs. As the input increases, the energy within the loop and the output signal also increases. This can cause several problems including increased energy passing through an integrator that may cause the integrator to clip, which in turn causes even more noise and distortion. Too much noise and distortion within the loop also eventually causes the output of the processor to enter an unstable state. With multi-order processors, this problem is even worse because the higher the order of the modulator, the output of the processor becomes unstable at lower input signals.
A multi-order sigma-delta digital processor with improved total harmonic distortion (THD) and noise characteristics is therefore needed.
SUMMARY OF THE INVENTION
The present invention relates to a mixed signal processing unit with non-linear feed-forward paths between sigma-delta modulator stages to improve total harmonic distortion (THD) and noise characteristics of the processor. Specifically the signal processing unit includes a first integrator stage configured to receive an input signal and configured to generate a first integrated signal in response thereto, a second integrator stage coupled to the first integrator stage and configured to generate a second integrated signal from the first integrated signal, a sampling stage coupled to the second integrator stage configured to sample the second integrated signal received from the second integrator stage at a sample frequency and to generated a logic signal, and a nonlinear feed-forward signal path coupled between the first integrator stage and the sampling stage. During operation, as the amplitude of the input signal increases, the energy provided through the feed-forward path increases and acts to overcome the gain of the second integrator stage which has the effect of bypassing the second integrator stage and effectively makes the mixed signal processing unit a first order modulator, thereby improving stability of the processor.
In alternative embodiments, a third integrator stage is provided and a second non-linear feedback stage is coupled between the second integrator stage and the sampling stage.
In this embodiment, as the amplitude of the input signal increases, initially the third integrator stage and then the second integrator stage are bypassed in the same manner. Thus the mixed signal processor thus successively becomes a second order modulator and then a first order modulator,thus reducing noise and distortion within the processor. Higher order modulators are also possible using standard sigma-delta design techniques.
In another embodiment of the invention, a method of reducing noise and distortion in a signal processor is disclosed. A first integrator stage is provided configured to receive an input signal and configured to generate a first integrated signal in response thereto. A second integrator stage is provide that is coupled to the first integrator stage and configured to generate a second integrated signal from the first integrated signal. A sampling stage is provided that is configured to sample the second integrated signal from the second integrator stage at a sample frequency and to generated a logic signal. Circuitry within the processor is provided arranged to effectively bypass the second integrator stage when the amplitude of the input signal increases.
In yet another embodiment, a mixed signal processor is disclosed. The mixed signal processor includes a modu
Beyer Weaver & Thomas LLP
Khai Nguyen
Tokar Michael
Tripath Technology Inc.
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