Mixed signal phase locked loop with process and temperature cali

Details Mixed signal phase locked loop with process and temperature cali Mixed signal phase locked loop with process and temperature cali

1996-10-23

1999-04-06

Grimm, Siegfried H.

Oscillators

Beat frequency

Frequency or amplitude adjustment or control

331 16, 331 17, 331 25, 331 34, 331 57, 331DIG2, H03L 7099, H03L 710

Patent

active

058924060

ABSTRACT:
A mixed signal phase locked loop is optimized for fast settling and low noise sensitivity. To this end, this device has a digital wide range delay line and a low gain per stage adjust. When first activated, the loop calibrates the digital delay line to its nominal delay characteristic. This delay line, together with the linear low gain per stage adjust, constitutes the internal oscillator of the phase locked loop. After achieving nominal delay, the oscillator uses the low gain per stage adjust to lock to a desired reference or a submultiple thereof. According to the preferred embodiment, the loop locks its internal 125 MHz oscillator to a 25 MHz reference. After achieving lock, the loop performs synchronous data recovery by locking to an incoming data stream, instead of the internal reference, and performing bit framing. In case of losing lock, the phase locked loop of the present invention is capable of recalibrating itself and regaining lock in under 3 microseconds.

REFERENCES:
patent: 5075640 (1991-12-01), Miyazawa
patent: 5212601 (1993-05-01), Wilson
patent: 5315271 (1994-05-01), Pascual et al.
patent: 5663991 (1997-09-01), Kelkar et al.

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