Mixed signal delay locked loop characterization engine

Details Mixed signal delay locked loop characterization engine Mixed signal delay locked loop characterization engine

2006-11-14

2006-11-14

Phan, Thai (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S002000, C327S156000, C716S030000, C714S731000

Reexamination Certificate

active

07136799

ABSTRACT:
A mixed signal delay locked loop characterization technique for automatically characterizing a mixed signal delay locked loop is provided. The technique tests the mixed signal delay locked loop using a top-down approach in order to ensure the robustness of the mixed signal delay locked loop. Top-level testing involves testing the performance of the mixed signal delay locked loop in different process corners, and the results obtained from the top-level testing are then used to test sub-components of the mixed signal delay locked loop.

REFERENCES:
patent: 5973526 (1999-10-01), Dabral
patent: 6037812 (2000-03-01), Gaudet
patent: 6388480 (2002-05-01), Stubbs et al.
patent: 6392456 (2002-05-01), Pyeon et al.
patent: 2001/0049812 (2001-12-01), Lutkemeyer
patent: 2004/0232962 (2004-11-01), Gomm et al.

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