Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2009-12-03
2010-11-16
Vu, Hung (Department: 2811)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S280000
Reexamination Certificate
active
07833842
ABSTRACT:
Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.
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Snider Gregory S.
Stewart Duncan
Williams R. Stanley
Hewlett--Packard Development Company, L.P.
Vu Hung
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