Mixed-radix serial/parallel multipliers

Details Mixed-radix serial/parallel multipliers Mixed-radix serial/parallel multipliers

1990-06-05

1992-09-22

Mai, Tan V.

Boots, shoes, and leggings

G06F 752

Patent

active

051503220

ABSTRACT:
A serial/parallel multiplier for the multiplication of a coefficient word with a data word of which the bits are broadcast n at a time where n is at least three. The structure comprises a plurality of pipes which where n is even each consists of a radix-4 encoder receiving two bits of the cluster and driving a partial product generator coupled to a respective carry-save array which forms the required two bits of the product by shifting and accumulation. For n equal to an odd number, the final sub-pipe consists of a radix-2 sub-pipe rather than a radix-4 sub-pipe and provides a single bit of the output, which consists of a cluster of n bits.

REFERENCES:
patent: 4546446 (1985-10-01), Machida
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4807175 (1989-02-01), Tokumaru et al.
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 4965762 (1990-10-01), Williams
Smith and Denyer, Serial Data Computation, Kluwer Academic Publishers, 1988, pp. 144-149.
Ercegovac, M. D. and Nash, J. G., "An Area-Time Efficient VLSI Design of a Radix-4 Multiplier", IEEE-ICCD 1983, pp. 684-687.

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