Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-06-02
2001-08-28
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185030
Reexamination Certificate
active
06282119
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains in general to a nonvolatile memory device capable of having data electrically written therein, and more particularly, a nonvolatile memory device capable of selectively writing one of a plurality of values therein, and a method thereof.
2. Description of the Related Art
An Electrically Programmable Read-Only Memory (“EPROM”) or a flash memory cell with a floating gate may be programmed by depositing electrons in the floating gate of the cell by electrons that tunnel from the cell substrate through a thin oxide layer disposed between the floating gate and the substrate. The tunneling electrons may be created by hot electron injection or Fowler Nordheim tunneling.
In a hot electron injection scheme, a high voltage is applied to the control gate of the cell and a low or zero voltage is applied to the drain region of the memory cell. Injection of electrons into the floating gate occurs when electrons in the channel region between the source and the drain regions of the cell attain an energy level higher than the barrier potential of the thin oxide layer. Some electrons will tunnel through the thin oxide layer and are injected into the floating gate, thereby depositing charges in the floating gate. For Fowler-Nordheim tunneling, a high voltage is applied to the control gate and a low voltage is applied to the drain region, and some electrons tunnel through the thin oxide layer to the floating gate.
However, not all electrons will attain an energy sufficient to tunnel through the thin oxide layer. The probability that an electron will tunnel through the thin oxide layer is proportional to the voltage difference between the control gate and the drain region. In addition, a charge proportional to the voltage difference between the control gate and drain will appear on the floating gate. The charge imposes an electric field on the channel region, known as the threshold voltage of the memory cell.
The threshold voltage determines whether a conventional memory cell is said to be storing any data or value. For example, a logic value of “0” is represented by setting a high threshold voltage and a logic value of “1” is represented by a low threshold voltage. Due to an increasing demand for memory storage capacity together with a decrease in available physical space, it is desirable to increase the memory storage capacity of individual memory cells. One attempt is described in U.S. Pat. No. 5,424,978 to Wada et al., which is hereby incorporated herein by reference.
Wada et al. describes a method and apparatus for storing more than two values within a single memory cell using hot electron injection. During programming, a high voltage pulse is sent to the drain of a memory cell. At the same time, a selected voltage from a stepped voltage signal is applied to the control gate. By applying the same voltage pulse to the drain at different times during the stepped voltage signal cycle, different levels of charges are stored in the floating gate. Therefore, each step of the stepped voltage signal produces a different threshold voltage in the memory cell, and, therefore, a plurality of “data” in the memory cell.
The method described in Wada et al. is limited in that the levels of the drain and control gate voltages are linked. For hot electron injection, the drain and control gate voltages must be set in a narrow requisite voltage range in relation to the other in order to create electrons having enough energy to tunnel through the thin oxide layer. The minimum requisite voltage is the threshold voltage of producing a charge on the floating gate, and the maximum requisite voltage is limited by the memory cell tolerance.
In general, the voltage applied to the control gate is fixed and the voltage applied to the drain is modulated to create different threshold voltage distributions. Because of cell tolerance, however, the voltage applied to the drain must be below the breakdown voltage to avoid the punch through effect. As a result, the allowable voltage difference between that applied to the drain and that applied to the floating gate is limited, thereby limiting the number of possible data that may be storage in the memory cell.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a nonvolatile memory device capable of storing more than two values in each of the memory cells and a method thereof that substantially obviates one or more problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structures and methods particularly pointed out in the written description and claims thereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the invention as embodied and broadly described, there is provided a nonvolatile semiconductor memory device including a memory cell array and capable of selectively writing one of a plurality of data values into individual memory cells in the memory cell array that includes rows and columns of memory cells, each of the memory cells having a control gate, a floating gate, a source and a drain. The device includes a first variable voltage oscillating circuit for producing a first stepped voltage to be applied to a selected memory cell, and a second variable voltage oscillating circuit for producing a second stepped voltage to be applied to the selected memory cell.
In one aspect of the invention, the first variable voltage oscillating circuit is, coupled to apply the first stepped voltage to the drain of the selected memory cell, and the second variable voltage oscillating circuit is coupled to apply the second stepped voltage to the control gate of the selected memory cell.
In another aspect of the invention, the device further includes an x-decoder coupled to the second variable voltage oscillating circuit for selecting a row of memory cells including the selected memory cell, and for applying the second stepped voltage to the control gates of the row of memory cells, a bit line selector coupled to the first variable voltage oscillating circuit, and a y-decoder coupled to the bit line selector for selecting a column of memory cells including the selected memory cell, and for applying the first stepped voltage to the drains of the column of memory cells.
In yet another aspect of the invention, the data values which can be written into each of the memory cells is equal to a number of ranges of values of charge which can be stored on the floating gate of the memory cell.
In still another aspect of the invention, the device additionally includes a timing circuit for producing trigger signals in response to a data value to be stored, wherein the first variable voltage oscillating circuit and the second variable voltage oscillating circuit initiate the first and second stepped variable voltage signals upon receiving the trigger signals, and hold the voltage signals at respective constant voltage values when the trigger signals stop.
Also in accordance with the present invention, there is provided a nonvolatile memory device that includes a memory array having a plurality of memory cells, each of the plurality of memory cells including a drain, a source, a control gate and a floating gate, a first variable voltage oscillating circuit coupled to the drain of a selected one of the plurality of memory cells for providing a first stepped voltage waveform, and a second variable voltage oscillating circuit coupled to the control gate of the selected one of the plurality of memory cells for providing a second stepped voltage waveform, wherein the first stepped voltage waveform and the second stepped voltage waveform cause the selected one of the plurality of memory cells to store one of a plurality of data values.
Further
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hoang Huan
Winbond Electronics Corporation
LandOfFree
Mixed program and sense architecture using dual-step voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mixed program and sense architecture using dual-step voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mixed program and sense architecture using dual-step voltage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2464282