Boots – shoes – and leggings
Patent
1987-11-12
1989-04-18
Harkcom, Gary V.
Boots, shoes, and leggings
364745, 364748, G06F 748
Patent
active
048232602
ABSTRACT:
Apparatus for performing mixed precision calculations in the floating point unit of a microprocessor from a single instruction opcode. 80-bit floating-point registers (44) may be specified as the source or destination address of a floating-point instruction. When the address range of the destination indicates (26) that a floating point register is addressed, the result of that operation is not rounded to the precision specified by the instruction, but is rounded (58) to extended 80-bit precision and loaded into the floating point register (FP-44). When the address range of the source indicates (26) that an FP register is addressed, the data is loaded from the FP register in extended precision, regardless of the precision specified by the instruction. In this way, real and long-real operations can be made to use extended precision numbers without explicitly specifying that in the opcode.
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patent: 4449196 (1984-05-01), Pritchard
patent: 4620292 (1986-10-01), Haginara et al.
patent: 4654785 (1987-03-01), Nishiyama
patent: 4748580 (1988-05-01), Ashton et al.
patent: 4763294 (1988-08-01), Fong
patent: 4779220 (1988-10-01), Nakiyama
patent: 4788655 (1988-11-01), Nakayama et al.
Imel Michael T.
Lai Konrad
Myers Glenford J.
Steck Randy
Valerio James
Harkcom Gary V.
Intel Corporation
Lamb Owen L.
Lynt Christopher H.
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