Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2006-09-19
2008-11-11
Baumeister, Bradley W. (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S628000, C257SE27112
Reexamination Certificate
active
07449767
ABSTRACT:
The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
REFERENCES:
patent: 4696097 (1987-09-01), McLaughlin et al.
patent: 4849371 (1989-07-01), Hansen et al.
patent: 4897704 (1990-01-01), Sakurai
patent: 4935864 (1990-06-01), Schmidt et al.
patent: 5371407 (1994-12-01), Goldman
patent: 5391914 (1995-02-01), Sullivan et al.
patent: 5455448 (1995-10-01), Benjamin
patent: 6100199 (2000-08-01), Joshi et al.
patent: 7033927 (2006-04-01), Cohen et al.
patent: 2002/0033189 (2002-03-01), Macris
patent: 2004/0256700 (2004-12-01), Doris et al.
patent: 2005/0277260 (2005-12-01), Cohen et al.
M. Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” Int. Electron Device Meeting (IEDM) Tech. Digest, p. 453, Dec. 2003.
K. L. Saenger, J.A. Ott, J.P. Desouza, and A. Reznicek, “Planar Substrate with Selected Semiconductor Crystal Orientations Formed by Localized Amorphization and Recrystallization of Stacked Template Layers,” U.S. Appl. No. 10/725,850.
Sangwood Pae et al., “Multiple Layers of Silicon-on-Insulator Islands Fabrication by Selective Epitaxial Growth,” IEEE Electron Device Lett., vol. 20(5), p. 194 (1999).
T.A. Langdo et al., “High Quality Ge on Si by Epitaxial Necking,” app. Phys. Lett., 76(25), p. 3700, (2000).
Wu, J.H., et al., “A Faraday Cage Isolation Structure for Substrate Crosstalk Suppression”, IEEE Microwave and Wireless Components Letters, vol. 11, No. 10, Oct. 2001; 3 pages.
Soh, H.T. et al., “Ultra-Low Reistance, Through-Wafer VIA (TWV) Technology and its Applications in Three Dimensional Structures on Silicon”, Japanese Journal of Applied Physics, vol. 38, 1999; 4 pages.
Wu, J., et al., “A High Aspect Ratio Silicon Substrate-Via Technology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation”, IEDM, 2000; 4 pages.
Edholm, et al., “Silicon-on-Diamond MOS-Transistors with Thermally Grown Gate Oxide”, IEEE, International Conference, Oct. 1997, pp. 30-31.
Hyongsok T. Soh, C. Patrick Yue, Anthony McCarthy, Changsup Ryu, Thomas H. Lee, S. Simon Wong and Calvin F. Quate, “Ultra-Low Resistance, Through-Wafer Cia (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon”, Jpn. J. Appl. Phys. vol. 38, pp. 2393-2396, 1999.
Cohen Guy M.
Reznicek Alexander
Saenger Katherine L.
Yang Min
Baumeister Bradley W.
International Business Machines - Corporation
Reames Matthew L
LandOfFree
Mixed orientation and mixed material... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mixed orientation and mixed material..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mixed orientation and mixed material... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4022305