Mixed mode power regulator circuitry for memory elements

Details Mixed mode power regulator circuitry for memory elements Mixed mode power regulator circuitry for memory elements

2011-01-11

2011-01-11

Laxton, Gary L (Department: 2838)

Electricity: power supply or regulation systems

External or operator controlled

Using a three or more terminal semiconductive device as the...

C323S268000, C323S274000, C323S284000

Reexamination Certificate

active

07868605

ABSTRACT:
Power regulator circuitry is provided for powering loads such as programmable memory element arrays on integrated circuits. The power regulator circuitry may have control circuitry that generates a first digital control signal to turn on and off a regulated power supply circuit and a second digital control signal to turn on and off a switch-based power supply circuit. The outputs of the regulated power supply circuit and switch-based power supply circuit may be connected to an output terminal for the power regulator circuitry. The first and second digital control signals may be used to ensure that the regulated power supply circuit is turned on before the switch-based power supply circuit is turned off. The switch-based power supply circuitry may contain serially connected transistors. The transistors may be turned off in an order that prevents latchup.

REFERENCES:
patent: 4473759 (1984-09-01), Mahabadi
patent: 4797584 (1989-01-01), Aguti
patent: 4816740 (1989-03-01), Maier
patent: 5212412 (1993-05-01), Atriss
patent: 5315178 (1994-05-01), Snider
patent: 5371709 (1994-12-01), Fisher et al.
patent: 5637991 (1997-06-01), Brown et al.
patent: 5959442 (1999-09-01), Hallberg et al.
patent: 6229288 (2001-05-01), Baretich et al.
patent: 6229289 (2001-05-01), Piovaccari et al.
patent: 6232893 (2001-05-01), Cliff et al.
patent: 6256681 (2001-07-01), Chang
patent: 6492850 (2002-12-01), Kato et al.
patent: 6515318 (2003-02-01), Tsunai
patent: 6717831 (2004-04-01), Rhee et al.
patent: 6954103 (2005-10-01), Yamauchi
patent: 6979983 (2005-12-01), Yen
patent: 7151656 (2006-12-01), Dvorak et al.
patent: 7205807 (2007-04-01), Svensson
patent: 7253596 (2007-08-01), Yamamoto et al.
patent: 7265601 (2007-09-01), Ahmad
patent: 7508177 (2009-03-01), Aiura et al.
U.S. Appl. No. 11/799,228, filed Apr. 30, 2007, Vest et al.
Liu, Ping-Chen, U.S. Appl. 11/824,838, filed Jul. 2, 2007.

Affiliated with

Also associated with

Rating

Mixed mode power regulator circuitry for memory elements does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mixed mode power regulator circuitry for memory elements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mixed mode power regulator circuitry for memory elements will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2686142