Mixed-mode PLL

Details Mixed-mode PLL Mixed-mode PLL

2009-03-16

2011-10-04

Gannon, Levi (Department: 2817)

Oscillators

With frequency adjusting means

With voltage sensitive capacitor

C331S00100A, C331S017000, C331S03600C, C375S376000

Reexamination Certificate

active

08031025

ABSTRACT:
A mixed-mode PLL is disclosed. The mixed-mode PLL comprises a digital sigma-delta modulator, a low pass filter, and a digital controlled oscillator. The digital sigma-delta modulator receives a fractional bit signal. The low pass filter is coupled to the digital sigma-delta modulator. The low pass filter receives an output signal of the digital sigma-delta modulator and converts the output signal to an analog control signal. The digital controlled oscillator comprises a varactor dynamically coupled to the low pass filter and receiving the analog control signal.

REFERENCES:
patent: 6208211 (2001-03-01), Zipper et al.
patent: 6606004 (2003-08-01), Staszewski et al.
patent: 7002415 (2006-02-01), Tsyrganovich
patent: 7046098 (2006-05-01), Staszewski
patent: 7719369 (2010-05-01), Kamath et al.
patent: 7750701 (2010-07-01), Ainspan et al.
patent: 2009/0097609 (2009-04-01), Chang et al.
patent: 2009/0243740 (2009-10-01), Rofougaran

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