Mixed dielectric process and nonvolatile memory device fabricate

Details Mixed dielectric process and nonvolatile memory device fabricate Mixed dielectric process and nonvolatile memory device fabricate

1982-02-26

1985-08-13

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29577C, 148 15, 148187, 357 232, 357 91, H01L 2122, H01L 2126

Patent

active

045341044

ABSTRACT:
A process for fabricating volatile and nonvolatile field effect devices on a common semiconductor wafer, and a unique composite structure for a nonvolatile memory device fabricated according to the process. A distinct feature of the process is the elimination of nitride from beneath any poly I layers while selectively retaining sandwiched and coextensive segments of nitride and poly II layers for the memory devices. In one form, the method commences with a wafer treated according to the general localized oxidation of silicon process, followed by a blanket enhancement implant and selectively masked depletion implants. The succeeding contact etch step is followed by a deposition of a poly I layer, a resistor forming implant and a patterned etch of the poly I layer. Thereafter, a first isolation oxide is grown, selective implants are performed to center the memory window, the memory area is etched, and the memory area is covered by a regrowth of a very thin memory oxide. The wafer is then coated with nitride and poly II, before undergoing a patterned plasma etch which successively and coextensively removes poly II and nitride in unwanted areas. Consequently, any nitride which remains is in a sandwiched arrangement with an overlying layer of poly II. The process inherently retains no nitride under any poly I layer, and thereby enhances the reliability of the complete IC. The composite nonvolatile memory device includes a poly II nonvolatile memory capacitor, a poly II depletion IGFET, and a poly I depletion IGFET over a single continuum of channel. The structural arrangement provides for selective access to the nonvolatile memory capacitor through the poly I IGFET during the write mode.

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patent: 4229755 (1980-10-01), Custode
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patent: 4306353 (1981-12-01), Jacobs et al.
patent: 4335505 (1982-06-01), Shibata et al.
patent: 4342149 (1982-08-01), Jacobs
patent: 4370798 (1983-02-01), Lieh et al.

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