Mixed delay locked loop circuit

Details Mixed delay locked loop circuit Mixed delay locked loop circuit

2001-12-27

2003-02-11

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C331SDIG002, C375S373000

Reexamination Certificate

active

06518807

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a mixed delay locked loop (DLL) circuit, and more particularly, to a circuit synchronizing an external reference signal and an output clock signal.
Whether a divisional clock signal is leading a reference signal or lagging behind the reference signal, it is an essential problem that a clock regeneration system is provided to a semiconductor memory device for stabilized locking within a short time in a high-speed computer. The regeneration is performed in all parts of the computer in order that all regenerated clock signals are generated with a minimum skew. Further, high resolution, rapid locking time and large frequency range are required in a graphic application such as pixel clock generation. Still further, a DDR DRAM circuit requires a minimum phase delay time less than ½ period of the reference signal.
A DLL circuit has been proposed as a method of solving the timing problem of an electric system. In particular, a projector can monitor a phase difference between the reference signal and the internal clock signal, related to the reference signal, using a DLL circuit. The phase difference between the reference signal and the internal clock signal causes a problem of response delay corresponding to the semiconductor memory device. As a result, the DLL has been employed to align the reference signal with the internal clock signal.
There are three types of DLL: digital, analog and mixed type. The mixed type DLL is disclosed in U.S. Pat. No. 6,242,955 B1 (Assignee: Silicon Magic Corporation, Appl.No.: 09/399,116, Filed: Sep. 20, 1999). As disclosed in the patent gazette, the mixed type DLL has advantages of rapid locking time, large frequency range and high resolution. However, it has a disadvantage that one cycle delay line is required to cover clock frequency to be employed. When one cycle delay line is employed, the delay shift is greatly increased as the result of noise. Further, power consumption and required range are also increased due to the delay line.
In digital DLL, movement caused by noise after locking is moved by unit delay since the delay line comprises unit delays. Therefore, there is a problem of large clock jitter.
SUMMARY OF THE INVENTION
Therefore, the present invention has been proposed in order to solve the above problems and an object of the present invention is to provide a DLL circuit wherein the delay shift is not greatly increased as the result of noise.
Another object of the present invention is to provide a DLL circuit having low power consumption and required range.
Still another embodiment of the present invention is to provide a DLL circuit wherein clock jitter is not greatly increased by movement as the result of noise after locking.
In order to accomplish the objects, the present invention comprises a mixed DLL circuit that includes a digital delay unit and analog delay unit. The digital delay unit has a digital half delay line comprising a plurality of unit delays, comparing phases of a reference clock signal inputted from the external and output clock signal generated by the mixed delay locked loop circuit to control delay time of the reference clock signal in the digital half delay line and to lock control on the digital half delay line when locking is accomplished between the reference clock signal and the output clock signal. The analog delay unit has an analog delay line, comparing phases of the reference clock signal and the output clock signal and converting the result into an analog signal and then, controlling the delay time of the output signal of the digital half delay line in the analog delay line by using the analog signal. It is desirable that the mixed DLL circuit further comprises an input buffer for generating and outputting a first internal clock signal having a signal level suitable for the mixed delay locked loop circuit and a second internal clock signal having a phase difference of 180° with the first internal clock signal by using the reference clock signal.
In addition to the digital half delay line, the digital delay unit further comprises: a first phase comparator for outputting a first phase comparison signal comparing phases of the first internal clock signal and the output clock signal and indicating the result; a first delay controller for generating a first delay control signal inputting the first phase comparison signal to control delay time in the digital half delay line; and a locking detector for inputting the first phase comparison signal and locking the first delay control signal if it is determined that the first internal clock signal and the output clock signal are locked. The first delay controller has a counter operating according to the first phase comparison signal, the counter being locked if it is determined that the first internal clock signal and the output clock signal are locked by the locking detector. One internal clock signal of the first internal clock signal and the second internal clock signal is selectively provided to the digital half delay line according to the first phase comparison signal and the output signal of the analog delay line is provided as the output clock signal of the mixed delay locked loop circuit.
In addition to the analog delay line, the analog delay unit further comprises: a second delay controller for comparing the phases of the reference clock signal and the output clock signal and outputting a second phase comparison signal indicating the result; and a digital/analog converter for converting the second phase comparison signal into an analog signal and providing the signal to the analog delay line to control the analog delay line.
According to the present invention, the delay line is shortened, thereby reducing the delay shift cuased by noise. Further, it has the advantages that power consumption and required range are also reduced and clock jitter is not greatly increased as the result of noise after locking.


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