Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
1996-07-15
2002-01-15
JeanPierre, Peguy (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S115000, C341S118000, C324S1540PB
Reexamination Certificate
active
06339388
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit in which an analog circuit and a digital circuit are mixed and further to a testing method thereof.
2. Description of the Prior Art
In recent years, the analog/digital mixed circuit technology in which an analog circuit and a digital circuit are integrated to form one chip has been considered to enhance the performances of an integrated circuit. In this case, it is necessary to test the actually fabricated semiconductor chip whether it can achieve desired functions/operations by using an LSI tester. That is, it is required to test the operations of wont only the analog circuit but the digital circuit.
Since, however, the conventional LSI tester for digital circuit is so constructed as to put emphasis only on the value of the logical signal and the timing of its appearance and cannot take its output waveform into consideration, an LSI tester dedicated to testing an analog circuit is required. As such an apparatus, one may point out two types, namely, an LSI tester which exclusively verifies only analog circuits, and an LSI tester for analog and digital circuits which can handle both the analog signal and the digital signal.
In the former apparatus, the digital test and the analog test have to be executed separately for the respective circuits, requiring tests repeated twice. Moreover, the whole circuit has to be constructed so as to permit separation of the digital circuit from the analog circuit, so that it brings about an increase in the chip area and the number of terminals. A configuration of a mixed analog/digital circuit which suppresses such a disadvantage to a possible minimum and increases the observability and the controllability is disclosed in, for example, Japanese Patent Application Laid Open No. 2-19780 (1990). However, in this configuration, an analog tester is absolutely necessary, and the need for twice tests remains unchanged.
In the latter, it is necessary to take the output waveform, in addition to the function of the digital tester, into consideration so that the LSI tester becomes expensive and the number of available testers has to be cut down drastically due to the cost. Because of this, the testing time and the testing cost for a chip of mixed analog and digital circuits are increased drastically compared with the case of a chip lacking the analog circuit, and one finds himself to be on the horns of a dilemma of imparting an added value and rise in the cost. Therefore, if a mixed chip of analog and digital circuits can also be tested using a digital tester alone, it will be extremely advantageous.
From such a viewpoint, a mixed analog/digital circuit as disclosed in, for example, Japanese Patent Application Laid Open No. 1-138478 (1989) has been proposed in the past.
Referring to
FIG. 6
showing a circuit configuration essentially equivalent to the above, a circuit constituted of a digital circuit
62
and a D/A converter
64
connected to the output of the digital circuit
62
is imagined in this circuit, wherein the function of outputting an analog signal is added to the ordinary function of the digital circuit.
In order to execute the test of this circuit with a digital tester, the analog output is further split into two parts, where an A/D converters
63
is connected to one of them to reconvert the analog output to get a digital signal again. If both the D/A converter
64
and the A/D converter
63
which is an additive function dedicated to the test are operating normally, a digital signal x immediately before D/A conversion and a digital signal z immediately after A/D conversion should be strictly equal, therefore, the test is accomplished by detecting the equivalence.
However, if the relation between the digital signal x and a signal y which is the result of its D/A conversion is represented by y=f(x), and the relation between the A/D converted signal z and the signal y is represented by z=g(y), then it follows that z=g(f(x)). The testing technique of the prior art shown in
FIG. 6
is aimed only at the verification of whether g is the inverse function of f, and is not aimed at ensuring the validity as an A/D converter and a D/A converter, namely, their linearity.
In the extreme case in which the data bus of the signal x and the data bus of the signal z are short-circuited, there is a possibility of letting the products pass the test as nondefective no matter what the signal y may be. Moreover, since it provides only the testing method of the D/A converter
64
on the output side, application of this testing method to a general analog/digital mixed integrated circuit was difficult.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a mixed analog/digital integrated circuit and a testing method thereof in which a test such as the verification of respective linearities of the installed A/D converter and D/A converter can be performed by itself.
An integrated circuit comprising, on a single semiconductor chip, a D/A converter receiving first digital data and converting said first digital data into a first analog signal having a first amplitude representative of a first value of said first digital data, first means operatively coupled to said D/A converter to receive said first analog signal for producing a second analog signal having a second amplitude that is K times as large as said first amplitude, said K being other than one, an A/D converter operatively receiving said second analog signal and converting said second analog signal into a second digital data having a second value representative of said second amplitude of said second analog signal, second means operatively coupled to said A/D converter to receive said second digital data for producing third digital data having a third value that is
1
/K times as large as said second value of said second digital data, and a comparator operatively coupled to receive said first and third digital data and comparing said first digital data with said third digital data.
It is preferable to constitute the first means by an attenuator. In this arrangement, the output of the D/A converter is supplied to the attenuator whose output is the supplied to the A/D converter. The output of the A/D converter is amplified in digital value by a multiplier as the second means. The output of the multiplier and the input of the D/A converter are finally compared with each other by the digital comparator. If the attenuation factor is 1/(0<&agr;<1), the multiplication factor is &agr;.
Assume that the relation between a digital signal x input to the D/A converter and the analog signal y output by the D/A converter is represented by y=f(x), and that the relation between the analog signal y input to the A/D converter and a digital signal z output by the A/D converter is represented by z=g(y).
The test according to the present invention is as follows. First, the analog multiplier and the digital multiplexer are set so that the analog signal from the D/A converter is transmitted directly to the A/D converter whose output is then compared with the input of the D/A converter. Mathematically speaking, it will be tested whether the relation
x=g(f(x))
holds for all x. If it is valid, then the relation
g·f=1,
that is,
f=g
−
1,
turns out to be verified. If the above does not hold, the specimen is decided as a defective unit.
If the product passes the first test, it will then be subjected to a second test as described below.
First, the analog multiplexer and the digital multiplexer are set so as to pass the analog signal from the D/A converter through the attenuator which multiplies the signal by X, to be input by the A/D converter, and then, the digital signal from the A/D converter via digital multiplying means which multiplies the signal by 1/&agr;, is compared with the input signal to the D/A converter. Mathematically speaking, it will be tested whether the relation
x=(1/&agr;)·g(&agr;·f(x))
holds for all x. If it is
Jean-Pierre Peguy
NEC Corporation
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